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general description the max1329/MAX1330 are smart data acquisition sys- tems (dass) based on a successive approximation register (sar) analog-to-digital converter (adc). these devices are highly integrated, offering an adc, digital- to-analog converters (dacs), operational amplifiers (op amps), voltage reference, temperature sensors, and analog switches in the same device. the max1329/MAX1330 offer a single adc with a refer- ence buffer. the adc is capable of operating in one of two user-programmable modes. in normal mode, the adc provides up to 12 bits of resolution at 312ksps. in dsp mode, the adc provides up to 16 bits of resolution at 1000sps. the adc accepts one external differential input or two external single-ended inputs as well as inputs from other circuitry on-board. an on-chip pro- grammable gain amplifier (pga) follows the analog inputs, reducing external circuitry requirements. the pga gain is adjustable from 1v/v to 8v/v. the max1329/MAX1330 operate from a 1.8v to 3.6v dig- ital power supply. shutdown and sleep modes are avail- able for power-saving applications. under normal operation, an internal charge pump boosts the supply voltage for the analog circuitry when the supply is < 2.7v. the max1329/MAX1330 offer four analog programmable i/os (apios) and four digital programmable i/os (dpios). the apios can be configured as general-pur- pose logic inputs and outputs, as a wake-up function, or as a buffer and level shifter for the serial interface to communicate with slave devices powered by the analog supply, av dd . the dpios can be configured as general- purpose logic inputs and outputs as well as inputs to directly control the adc conversion rate, the analog switches, the loading of the dacs, wake-up, sleep, and shutdown modes, and as an interrupt for when the ana- log-to-digital conversion is complete. the max1329 includes dual 12-bit force-sense dacs with a programmable reference buffer and one op amp. the MAX1330 provides one 12-bit force-sense dac with a programmable reference buffer and two op amps. for the max1329/MAX1330, a 16-word dac fifo can be used with the daca for direct digital synthesis (dds) of waveforms. the 4-wire serial interface is compatible with spi?, qspi?, and microwire?. applications battery-powered and portable devices electrochemical and optical sensors medical instruments industrial control data acquisition systems low-cost codecs features ? 1.8v to 3.6v single digital supply operation ? internal charge pump for analog circuits (2.7v to 5.5v) ? 12-bit sar adc 12 bits, 312ksps, no missing codes 16 bits, 1000sps, dsp mode 16-word fifo and 20-bit accumulator pga with gains of 1, 2, 4, and 8 unipolar and bipolar modes 16-input differential multiplexer ? dual 12-bit force-sense dacs 16-word fifo (daca only) ? independent voltage references for adc and dacs internal 2.5v reference adjustable reference buffers provide 1.25v, 2.048v, or 2.5v ? system support adc alarm register uncommitted op amps dual spdt analog switches internal/external temperature sensor internal oscillator with clock i/o digital programmable i/o analog programmable i/o programmable interrupts accurate supply voltage measurement programmable dual voltage monitors ? spi-/qspi-/microwire-compatible, 4-wire serial interface ? space-saving, 6mm x 6mm, 40-pin thin qfn package max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ________________________________________________________________ maxim integrated products 1 19-4252; rev 1; 10/08 for pricing delivery, and ordering information please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin-package m a x1 3 2 9 be tl+ -40c to +85c 40 thin qfn-ep** m a x1 3 3 0 be tl+ * -40c to +85c 40 thin qfn-ep** spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. * future productcontact factory for availability. ** ep = exposed pad. + denotes a lead-free/rohs-compliant package. pin configurations appear at end of data sheet.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd .........................................................-0.3v to +6v dv dd to dgnd.........................................................-0.3v to +6v analog inputs to agnd....................................-0.3v to the lower of (av dd + 0.3v) or +6v digital inputs to dgnd.....................................-0.3v to the lower of ( dv dd + 0.3v) or +6v analog outputs to agnd .................................-0.3v to the lower of (av dd + 0.3v) or +6v digital outputs to dgnd ..................................-0.3v to the lower of (dv dd + 0.3v) or 6v agnd to dgnd.................................................... -0.3v to +0.3v continuous current into any pin.......................................50ma continuous power dissipation (t a = +70c) 40-pin thin qfn (derate 37mw/c above +70c) ....2963mw operation temperature range............................-40c to +85c storage temperature range .............................-65c to +150c junction temperature ......................................................+150c lead temperature (soldering, 10s) ................................+300c electrical characteristics (dv dd = 1.8v to 3.6v, av dd = 2.7v to 5.5v, v refdac = v refadc = 2.5v, external reference; 10f capacitor at refadc and refdac; 0.01f capacitor at refadj; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units adc resolution no missing codes 12 bits dsp-mode resolution 256 oversampling, dither enabled 16 bits integral nonlinearity inl normal mode (note 1) 1 lsb 12 differential nonlinearity dnl normal mode (note 1) 1 lsb 12 offset error (note 1) 4 mv offset drift 1.5 v/c gain = 1 0.1 gain = 2, 4 1.5 gain error (excluding reference) (note 1) gain = 8 2.5 % fs gain temperature coefficient excluding reference 0.8 ppm/c unipolar mode, gain = 1, 2, 4, 8 0 + v r e f ad c / gain voltage range bipolar mode, gain = 1, 2, 4, 8 -v refadc / (2 x gain) + v r e f ad c / (2 x gain) v absolute input voltage range agnd av dd v input leakage current into analog inputs (note 2) 0.5 1 na gain = 1, 2 24 input capacitance gain = 4, 8 48 pf gain = 1, 2 0.6 acquisition time t acq gain = 4, 8 1.2 s conversion time t conv 12 clocks 2.4 s conversion clock frequency 0.1 5.0 mhz normal operation mode, adc converting at 234ksps 325 adc supply current (note 3) fast power-down mode, adc converting at 234ksps 210 a aperture delay t ad 30 ns
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor _______________________________________________________________________________________ 3 electrical characteristics (continued) (dv dd = 1.8v to 3.6v, av dd = 2.7v to 5.5v, v refdac = v refadc = 2.5v, external reference; 10f capacitor at refadc and refdac; 0.01f capacitor at refadj; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units aperture jitter t aj 50 ps gain = 1, 2; dv dd 2.7v, av dd 5.0v 312 gain = 4, 8; dv dd 2.7v, av dd 5.0v 263 gain = 1, 2 234 sample rate gain = 4, 8 200 ksps power-supply rejection psr av dd = 2.7v to 5.5v, full-scale input 0.06 0.5 mv/v turn-on time supply and reference have settled 1 s adc dynamic accuracy (10khz sine wave, v in = 2.5v p-p , f sample = 234ksps, gain = 1) signal-to-noise plus distortion sinad 71 db total harmonic distortion thd up to the 5th harmonic 82 db spurious-free dynamic range sfdr 84 db channel-to-channel crosstalk 100 db full-power bandwidth fpbw -3db point 4 mhz dac (r l = 5k ? , c l = 200pf, tested in unity gain, unless otherwise noted) resolution 12 bits differential nonlinearity dnl guaranteed monotonic (note 4) 1.0 lsb integral nonlinearity inl (note 4) 1 8 lsb offset error code = 0x000 (tested at 0x032) 2.5 30 mv offset-error temperature coefficient due to amplifier 7 v/c gain error code = 0xfff 0 5 % fs gain-error temperature coefficient excluding reference drift 7 ppm/c output voltage range no load agnd av dd v output slew rate c l = 200pf 0.5 v/s output settling time code = 0x400 to 0xc00 (note 2) 4 10 s fb_ input bias current (note 2) 0.1 1 na fb_ switch resistance 200 ? fb_ switch turn-on/-off time 40 ns fb_ switch off isolation f = 10khz 100 db fb_ switch charge injection 1pc dac-to-dac crosstalk 0.5 nv-s sink 13 short-circuit current source 50 ma dc output impedance code = 0x800 0.8 ? power-up time 0.5 lsb settling to 0x800 5 s power-supply rejection psr av dd = 2.7v to 5.5v 1 mv/v charge-pump output feedthrough code = 0x800, buffer on, r l = 5k ? , c l = 200pf 100 v rms
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 4 _______________________________________________________________________________________ electrical characteristics (continued) (dv dd = 1.8v to 3.6v, av dd = 2.7v to 5.5v, v refdac = v refadc = 2.5v, external reference; 10f capacitor at refadc and refdac; 0.01f capacitor at refadj; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units power-down output leakage current 100 na supply current per dac no load (note 3) 70 a internal reference (10? capacitor at refadc and refdac, 0.01? capacitor at refadj) t a = + 25 c , are f< 1:0> = d re f< 1:0> = 01 1.225 1.250 1.275 t a = + 25 c , are f< 1:0> = d re f< 1:0> = 10 2.007 2.048 2.089 output voltage at refadc and refdac t a = + 25 c , are f< 1:0> = d re f< 1:0> = 11 2.450 2.500 2.550 v output-voltage temperature (note 2) 10 75 ppm/c source 40 refadc and refdac output short-circuit current sink 13 ma refadc and refdac line regulation 100 600 v/v i source = 0a to 500a, t a = +25c 10 load regulation i sink = 0a to 80a, t a = +25c 10 v/a long-term stability t a = +25c 100 ppm/ 1000hrs turn-on time at refadj 2 ms turn-off time 100 ns internal reference 445 refadc buffer 270 refer ence s up p l y c ur r ent ( n ote 3) refdac buffer 270 a external reference at refadj aref<1:0> = dref<1:0> = 11 1.225v av dd - 0.1v aref<1:0> = dref<1:0> = 10 1.496v to av dd - 0.1v external reference input voltage range aref<1:0> = dref<1:0> = 01 2.450v to av dd - 0.1v v input resistance 50 75 k ? aref<1:0> = 01 1 aref<1:0> = 10 0.8192 refadc buffer gain aref<1:0> = 11 0.5 v/v dref<1:0> = 01 1 dref<1:0> = 10 0.8192 refdac buffer gain dref<1:0> = 11 0.5 v/v minimum capacitive bypass refadj to agnd 10 nf
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor _______________________________________________________________________________________ 5 electrical characteristics (continued) (dv dd = 1.8v to 3.6v, av dd = 2.7v to 5.5v, v refdac = v refadc = 2.5v, external reference; 10f capacitor at refadc and refdac; 0.01f capacitor at refadj; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units external reference at refadc external reference input voltage range agnd av dd v refadc input resistance 50 75 k ? refadc input current v refadc = 2.5v, 300ksps 30 40 a turn-on time refadc buffer, c refadc = 1f 75 s shutdown refadc input current 0.01 1.0 a minimum capacitive bypass refadc to agnd 10 f external reference at refdac refdac input voltage range agnd av dd v max1329 64 90 180 refdac input resistance MAX1330 128 180 360 k ? max1329, v refdac = 2.5v 28 86 refdac input current MAX1330, v refdac = 2.5v 14 43 a turn-on time refdac buffer 75 s shutdown refdac input current 0.1 1 a minimum capacitive bypass refdac to agnd 10 f multiplexer absolute input voltage range agnd av dd v absolute input leakage current ( ag n d + 100m v ) < v a in _ < ( av d d - 100m v ) ( n ote 2) 0.01 1 na adc gain = 1, 2 24 input capacitance adc gain = 4, 8 48 pf on resistance 340 ? internal temperature sensor t a = +25c 0.25 internal sensor measurement error ( n ote 5) t a = -40c to +85c 3 c t a = +25c 0.4 t a = 0c to +70c 2 external sensor measurement error ( n ote 5) t a = -40c to +85c 3 c
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 6 _______________________________________________________________________________________ electrical characteristics (continued) (dv dd = 1.8v to 3.6v, av dd = 2.7v to 5.5v, v refdac = v refadc = 2.5v, external reference; 10f capacitor at refadc and refdac; 0.01f capacitor at refadj; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units temperature resolution v refadc = 2.5v 1/8 c/lsb external-diode drive ratio i drivemin = 4a, i drivemax = 68a 17:1 temperature-sensor supply current not including adc current (note 3) 100 a temperature-sensor conversion time 307 clocks per measurement, master clock = 5.00mhz 65 s charge pump input voltage dv dd 1.8 3.6 v dv dd = 1.8v to 3.0v, vm2cp<2:0> = 001 2.85 3.0 3.20 dv dd = 2.2v to 3.6v, vm2cp<2:0> = 010 3.75 4.0 4.30 no-load output voltage av dd dv dd = 2.7v to 3.6v, vm2cp<2:0> = 011 4.80 5.0 5.40 v output current including internal current (table 32) 25 ma no-load supply current dv dd = 2.7v, av dd = 4v, 39khz clock 250 a switching frequency 39 78 khz switch turn-on/-off time between dv dd to av dd , charge pump off 40 ns switch impedance shorts dv dd to av dd , charge pump off 25 50 ? efficiency 25ma load, dv dd = 1.8v, av dd = 3.0v, 39khz clock 80 % dv dd voltage monitor (vm1) supply voltage range 1.0 3.6 v vm1<1:0> = 0x, rst1 input 1.80 1.865 1.93 trip threshold (dv dd falling) v dth vm1<1:0> = x0, rst2 input 2.65 2.750 2.90 v vm1<1:0> = 0x, rst1 input 15 hysteresis v dhys vm1<1:0> = x0, rst2 input 22.5 mv reset timeout period v dvdd = v dth + v dhys 170 ms turn-on time dv dd = 1.8v, enabled by vm1 <1:0> 2 ms av dd voltage monitor (vm2) supply voltage range 1.0 5.5 v vm2cp<1:0> = 01 2.53 2.775 2.975 vm2cp<1:0> = 10 3.4 3.700 3.925 trip threshold (av dd falling) (note 6) v ath vm2cp<1:0> = 11 4.25 4.625 4.925 v vm2cp<1:0> = 01 22.5 vm2cp<1:0> = 10 30 hysteresis v ahys vm2cp<1:0> = 11 37.5 mv
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor _______________________________________________________________________________________ 7 electrical characteristics (continued) (dv dd = 1.8v to 3.6v, av dd = 2.7v to 5.5v, v refdac = v refadc = 2.5v, external reference; 10f capacitor at refadc and refdac; 0.01f capacitor at refadj; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units turn-on time av dd = 2.7v, enabled by vm2cp<1:0> 2 ms internal oscillator clock frequency t a = t min to t max 3.5758 3.6864 3.7970 mhz turn-off delay using clock at clkio pin, odly = 1 1024 clocks turn-on time 200 ns supply current (note 7) 120 a switches (spdt) av dd = 2.7v to 5.5v 140 200 on resistance av dd = 4.5v to 5.5v 90 120 ? on-resistance match 15 ? on-resistance flatness over analog voltage range 12 ? analog voltage range agnd av dd v turn-on/-off time break-before-make for spdt configuration 50 ns leakage current agnd + 100mv < v sn_ < av dd - 100mv (note 2) 0.08 1 na off isolation f = 10khz 100 db charge injection 1pc input capacitance 2pf operational amplifier (r l = 10k ? , c l = 200pf) input bias current (note 2) 0.3 1 na input offset voltage v os 2 20 mv input offset drift ? v os 10 v/c common-mode rejection ratio cmrr agnd + 100mv < v cm < av dd - 100mv 75 db phase margin 60 degrees charge-pump output feedthrough 100 v p-p common-mode input voltage range agnd av dd v no load agnd av dd 10k ? load 0.1 av dd - 0.1 output voltage range 100k ? load 0.1 av dd - 0.1 v gain bandwidth product 1 mhz slew rate 0.5 v/s av dd = 2.7v to 5.5v 140 200 osw_ switch resistance av dd = 4.5v to 5.5v 90 120 ? osw_ switch turn-on/-off time 50 ns
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 8 _______________________________________________________________________________________ electrical characteristics (continued) (dv dd = 1.8v to 3.6v, av dd = 2.7v to 5.5v, v refdac = v refadc = 2.5v, external reference; 10f capacitor at refadc and refdac; 0.01f capacitor at refadj; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units osw_ switch charge injection 1pc input noise voltage density f in_ = 1khz 330 nv/ hz input noise voltage f in_ = 0.1hz to 10hz 9 v rms power-down output leakage 10 na power-supply rejection ratio av dd = 2.7v to 5.5v 65 100 db supply current per amplifier (note 3) 70 a turn-on time 5s source 50 short-circuit current sink 13 ma dc output impedance a v = 1v/v 0.2 ? digital inputs (din, sclk, cs ) input high voltage v ih 0.7 x dv dd v input low voltage v il 0.3 x dv dd v input hysteresis dv dd = 3v 200 mv input leakage current v in = 0 or dv dd 0.01 10 a digital outputs (dout, rst1 , rst2 ) i sink = 1ma, dv dd = 2.7v to 3.6v 0.4 output low voltage v ol i sink = 200a, dv dd = 1.8v to 3.6v 0.4 v i source = 0.2ma, dv dd = 2.7v to 3.6v 0.8 x dv dd output high voltage v oh i source = 100a, dv dd = 1.8v to 3.6v 0.8 x dv dd v dout three-state leakage 0.01 10 a dout three-state capacitance (note 2) 15 pf i sink = 1ma, dv dd = 2.7v to 3.6v 0.4 rst1 , rst2 open-drain output low voltage i sink = 200a, dv dd = 1.8v to 3.6v 0.4 v rst1 , rst2 open-drain output leakage current (note 2) 0.13 100 na digital i/o (dpio1?pio4, clkio) i sink = 2ma, dv dd = 2.7v to 3.6v 0.4 output low voltage i sink = 1ma, dv dd = 1.8v to 3.6v 0.4 v i source = 2ma, dv dd = 2.7v to 3.6v 0.8 x dv dd output high voltage i source = 1ma, dv dd = 1.8v to 3.6v 0.8 x dv dd v
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor _______________________________________________________________________________________ 9 electrical characteristics (continued) (dv dd = 1.8v to 3.6v, av dd = 2.7v to 5.5v, v refdac = v refadc = 2.5v, external reference; 10f capacitor at refadc and refdac; 0.01f capacitor at refadj; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units input high voltage 0.7 x dv dd v dpio1Cdpio4 0.3 x dv dd input low voltage clkio 0.25 x dv dd v input hysteresis dv dd = 3v 110 mv three-state leakage 0.01 1 a three-state capacitance (note 2) 15 pf dpio_ pullup resistance 0.5 m ? analog i/o (apio1?pio4) i sink = 2ma, av dd = 2.7v to 5.5v 0.4 output low voltage i sink = 1ma, av dd = 1.8v to 5.5v 0.4 v i source = 2ma, av dd = 2.7v to 5.5v 0.8 x av dd output high voltage i source = 1ma, av dd = 1.8v to 5.5v 0.8 x av dd v av dd = 2.7v to 5.5v 0.7 x av dd input high voltage av dd = dv dd = 1.8v to 3.6v 0.7 x av dd v av dd = 2.7v to 5.5v 0.3 x av dd input low voltage av dd = dv dd = 1.8v to 3.6v 0.3 x av dd v av dd = 3v 120 input hysteresis av dd = 5v 160 mv three-state leakage 0.01 10 a three-state capacitance (note 2) 15 pf pullup resistance 0.5 m ? power requirements dv dd supply voltage range 1.8 3.6 v av dd supply voltage range 2.7 5.5 v run (all on, except charge pump) 3.75 7.5 ma supply current (note 8) sleep (1.8v or 2.7v monitor on) 1 2.5 a shutdown current all off 0.5 1 a
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 10 ______________________________________________________________________________________ timing characteristics (dv dd = 1.8v to 3.6v, av dd = 2.7v to 5.5v, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units serial-interface timing parameters (dv dd = 2.7v to 3.6v) (figures 1 and 2) sclk operating frequency f op 0 20 mhz sclk cycle time t cyc 50 ns din to sclk setup t ds 15 ns din to sclk hold t dh 0ns sclk fall to output data valid t do 20 ns cs fall to output enable t dv 24 ns cs rise to output disable t tr 24 ns cs to sclk rise setup t css 15 ns cs to sclk rise hold t csh 0ns sclk pulse-width high t ch 20 ns sclk pulse-width low t cl 20 ns serial-interface timing parameters (dv dd = 1.8v to 3.6v) (figures 1 and 2) sclk operating frequency f op 0 10 mhz sclk cycle time t cyc 100 ns din to sclk setup t ds 30 ns din to sclk hold t dh 0ns sclk fall to output data valid t do 40 ns cs fall to output enable t dv 48 ns cs rise to output disable t tr 48 ns cs to sclk rise setup t css 30 ns cs to sclk rise hold t csh 0ns sclk pulse-width high t ch 40 ns sclk pulse-width low t cl 40 ns digital programmable i/o timing parameters (dpio1?pio4, dv dd = 2.7v to 3.6v, c l = 20pf) spi write to dpio output valid t sd from last sclk rising edge 50 ns dpio rise/fall input to interrupt asserted delay t di interrupt programmed on rst1 and/or rst2 , corresponding status bits unmasked 55 ns dpio input to analog block delay t da when controlling adc, dacs, or switches 40 ns digital programmable i/o timing parameters (dpio1?pio4, dv dd = 1.8v to 3.6v, c l = 20pf) spi write to dpio output valid t sd from last sclk rising edge 100 ns dpio rise/fall input to interrupt asserted delay t di interrupt programmed on rst1 and/or rst2 , corresponding status bits unmasked 150 ns dpio input to analog block delay t da when controlling adc, dacs, or switches 50 ns analog programmable i/o timing parameters (apio1?pio4, dv dd = 2.7v to 3.6v, av dd = 2.7v to 5.5v, c l = 20pf) spi write to apio output valid t sd from last sclk rising edge 50 ns apio rise/fall input to interrupt asserted delay t di interrupt programmed on rst1 and/or rst2 , corresponding status bits unmasked 50 ns cs to apio4 propagation delay t dca ap4md<1:0> = 11 35 ns
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 11 timing characteristics (continued) (dv dd = 1.8v to 3.6v, av dd = 2.7v to 5.5v, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units sclk to apio3 propagation delay t dsa ap3md<1:0> = 11, cs is high 30 ns din to apio2 propagation delay t dda ap2md<1:0> = 11, cs is high 25 ns apio1 to dout propagation delay t dad ap1md<1:0> = 11, cs is high 20 ns spi-mode propagation delay matching t dm among apio4, apio3, apio2, and apio1 10 ns analog programmable i/o timing parameters (apio1?pio4, dv dd = 1.8v to 3.6v, av dd = 2.7v to 5.5v, c l = 20pf) spi write to apio output valid t sd from last sclk rising edge 100 ns apio rise/fall input to interrupt asserted delay t di interrupt programmed on rst1 and/or rst2 , corresponding status bits unmasked 175 ns cs to apio4 propagation delay t dca ap4md<1:0> = 11 60 ns sclk to apio3 propagation delay t dsa ap3md<1:0> = 11, cs is high 50 ns din to apio2 propagation delay t dda ap2md<1:0> = 11, cs is high 50 ns apio1 to dout propagation delay t dad ap1md<1:0> = 11, cs is high 80 ns spi-mode propagation delay matching t dm among apio4, apio3, apio2, and apio1 30 ns note 1: adc inl and dnl, offset, and gain are tested at dv dd = 1.8v, av dd = 2.7v, f sample = 234ksps to guarantee performance at f sample = 312ksps, dv dd 2.7v and av dd 5.0v. note 2: guaranteed by design. not production tested. note 3: av dd supply current contribution for this module. note 4: dnl and inl are measured between code 115 and 4095. note 5: temperature sensor accuracy is tested using a 2.5084v reference applied to refadj. note 6: the maximum trip levels for the av dd monitor are 5% below the typical charge-pump output value. the charge-pump output voltage and the trip thresholds track to prevent tripping at -5% below the typical charge-pump output value. note 7: dv dd supply current contribution for this module. note 8: the normal operation and sleep mode supply currents are measured with no load on dout, sclk idle, and all digital inputs at dgnd or dv dd . clkio runs in normal mode operation and idle in sleep mode.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 12 ______________________________________________________________________________________ typical operating characteristics (av dd = 5.0v, v refadc = v refdac = 2.5v for dv dd = 3.0v; t a = +25c, unless otherwise noted.) 0 0.2 0.6 0.4 0.8 1.0 1.5 2.5 3.0 2.0 3.5 4.0 4.5 5.0 5.5 static digital supply current vs. digital suply voltage (everything on) max1329 toc01 dv dd (v) i dvdd (ma) t a = +25c t a = +85c t a = -40c 0 0.50 0.25 1.00 0.75 1.25 1.50 1.75 2.00 1.5 2.5 3.0 2.0 3.5 4.0 4.5 5.0 5.5 static digital supply current vs. digital supply voltage (only vm1a on) max1329 toc02 dv dd (v) i dvdd ( a) t a = +25c t a = +85c t a = -40c 0 0.50 0.25 1.00 0.75 1.25 1.50 1.75 2.00 1.5 2.5 3.0 2.0 3.5 4.0 4.5 5.0 5.5 static digital supply current vs. digital supply voltage (shutdown) max1329 toc03 dv dd (v) i dvdd ( a) t a = +25c t a = +85c t a = -40c 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 2.5 3.5 3.0 4.0 4.5 5.0 5.5 static analog supply current vs. analog supply voltage (everything on) max1329 toc04 av dd (v) i avdd (ma) t a = +25c t a = +85c t a = -40c 0 200 600 400 800 1000 2.5 3.5 3.0 4.0 4.5 5.0 5.5 static analog supply current vs. analog supply voltage (only vm1a and vm1b on) max1329 toc05 av dd (v) i avdd (na) t a = +25c t a = +85c t a = -40c 0 200 600 400 800 1000 2.5 3.5 3.0 4.0 4.5 5.0 5.5 static analog supply current vs. analog supply voltage (shutdown) max1329 toc06 av dd (v) i avdd (na) t a = +25c t a = +85c t a = -40c f osc error vs. digital supply voltage max1329 toc07 dv dd (v) f osc error (%) 3.4 3.2 2.8 3.0 2.2 2.4 2.6 2.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 1.8 3.6 nominal f osc = 3.6864mhz (0% value) t a = -40 c t a = +85 c t a = +25 c adc integral nonlinearity vs. temperature max1329 toc08 temperature ( c) inl (lsb) 60 35 10 -15 0.3 0.4 0.5 0.6 0.7 0.8 0.2 -40 85 f conv = 234ksps av dd = 2.7v av dd = 5.5v av dd = 5.0v adc integral nonlinearity vs. temperature max1329 toc09 temperature ( c) inl (lsb) 60 35 10 -15 0.3 0.4 0.5 0.6 0.7 0.8 0.2 -40 85 av dd = 5.5v av dd = 5.0v f conv = 312ksps
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 13 typical operating characteristics (continued) (av dd = 5.0v, v refadc = v refdac = 2.5v for dv dd = 3.0v; t a = +25c, unless otherwise noted.) adc differential nonlinearity vs. digital input code (av dd = 3.0v) max1329 toc10 digital input code dnl (lsb) 3072 2048 1024 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 f sample = 234ksps adc integral nonlinearity vs. digital input code (av dd = 3.0v) max1329 toc11 digital input code inl (lsb) 3072 2048 1024 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 f sample = 234ksps 90 100 95 110 105 115 120 adc supply current vs. analog supply voltage max1329 toc12 av dd (v) i avdd ( a) 2.5 3.5 4.0 3.0 4.5 5.0 5.5 adc supply current vs. conversion rate max1329 toc13 0 50 150 100 300 350 250 200 400 i avdd ( a) 0 100 150 50 200 250 300 conversion rate (ksps) b = normal mode av dd = 5v, v refdac = 2.5v e = normal mode av dd = 3v, v refadc = 1.25v c = burst mode av dd = 5v, v refdac = 2.5v f = burst mode av dd = 3v, v refadc = 1.25v d = fast power-down av dd = 3v, v refadc = 1.25v a = fast power-down av dd = 5v, v refdac = 2.5v a b c d e f 0 0.1 0.3 0.2 0.4 0.5 -40 10 -15 35 60 85 adc offset voltage vs. temperature max1329 toc14 temperature ( c) offset (mv) av dd = 2.7v av dd = 5.5v 0.40 0.42 0.46 0.44 0.48 0.50 adc offset error vs. supply voltage max1329 toc15 av dd (v) offset (mv) 2.7 3.7 4.7
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 14 ______________________________________________________________________________________ 0.020 0.021 0.022 0.023 2.7 3.7 4.7 adc gain error vs. supply voltage max1329 toc17 av dd (v) gain error (%) a v = 1 -120 -80 -100 -40 -60 -20 0 06080 20 40 100 120 adc 4096-point fft plot max1329 toc18 frequency (khz) voltage (db) f in = 10.261khz fs = 253.95ksps thd = 82.86db sfdr = 84.74db sinad = 70.98db 10.0 11.0 10.5 12.0 11.5 12.5 13.0 120 220 170 270 320 adc enob vs. frequency max1329 toc19 conversion rate (ksps) effective number of bits (enob) typical operating characteristics (continued) (av dd = 5.0v, v refadc = v refdac = 2.5v for dv dd = 3.0v; t a = +25c, unless otherwise noted.) 0 0.01 0.03 0.02 0.04 0.05 -40 10 -15 35 60 85 adc gain error vs. temperature max1329 toc16 temperature ( c) error (%) av dd = 2.7v av dd = 5.5v a v = 1
max1329/MAX1330 adc reference voltage (1.25v) vs. analog supply voltage max1329 toc23 av dd supply voltage (v) v refadc (v) 1.246 1.247 1.248 1.249 1.250 1.251 1.252 1.253 1.254 1.255 1.245 5.0 4.5 3.0 3.5 4.0 2.5 5.5 t a = -40 c t a = +85 c t a = +25 c 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 15 adc reference voltage (1.25v) vs. load current max1329 toc20 400 300 0 100 200 1.2485 1.2490 1.2495 1.2500 1.2505 1.2510 1.2515 1.2520 1.2480 -100 500 a b c d e f i refadc ( a) a: t a = -40 c, av dd = 5v, dv dd = 3v b: t a = -40 c, av dd = 3v, dv dd = 2v c: t a = +25 c, av dd = 5v, dv dd = 3v d: t a = +25 c, av dd = 3v, dv dd = 2v e: t a = +85 c, av dd = 5v, dv dd = 3v f: t a = +85 c, av dd = 3v, dv dd = 2v v refadc (v) adc reference voltage (2.048v) vs. load current max1329 toc21 400 300 0 100 200 2.042 2.044 2.046 2.048 2.050 2.052 2.054 2.056 2.040 -100 500 a b c d e f i refadc ( a) v refadc (v) a: t a = -40 c, av dd = 5v, dv dd = 3v b: t a = -40 c, av dd = 3v, dv dd = 2v c: t a = +25 c, av dd = 5v, dv dd = 3v d: t a = +25 c, av dd = 3v, dv dd = 2v e: t a = +85 c, av dd = 5v, dv dd = 3v f: t a = +85 c, av dd = 3v, dv dd = 2v adc reference voltage (2.5v) vs. load current max1329 toc22 2.492 2.494 2.496 2.498 2.500 2.502 2.504 2.506 2.508 2.510 2.490 400 300 0 100 200 -100 500 a b c d e f i refadc ( a) v refadc (v) a: t a = -40 c, av dd = 5v, dv dd = 3v b: t a = -40 c, av dd = 3v, dv dd = 2v c: t a = +25 c, av dd = 5v, dv dd = 3v d: t a = +25 c, av dd = 3v, dv dd = 2v e: t a = +85 c, av dd = 5v, dv dd = 3v f: t a = +85 c, av dd = 3v, dv dd = 2v typical operating characteristics (continued) (av dd = 5.0v, v refadc = v refdac = 2.5v for dv dd = 3.0v; t a = +25c, unless otherwise noted.)
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 16 ______________________________________________________________________________________ adc reference voltage (2.5v) vs. analog supply voltage max1329 toc25 av dd supply voltage (v) v refadc (v) 2.492 2.494 2.496 2.498 2.500 2.502 2.504 2.506 2.508 2.510 2.490 5.0 4.5 3.0 3.5 4.0 2.5 5.5 t a = -40 c t a = +85 c t a = +25 c 2.042 2.043 2.044 2.045 2.046 2.047 2.048 2.049 2.050 2.051 2.052 2.053 2.054 2.055 2.041 adc reference voltage (2.048v) vs. analog supply voltage max1329 toc24 av dd supply voltage (v) v refadc (v) 5.0 4.5 3.0 3.5 4.0 2.5 5.5 t a = -40 c t a = +85 c t a = +25 c typical operating characteristics (continued) (av dd = 5.0v, v refadc = v refdac = 2.5v for dv dd = 3.0v; t a = +25c, unless otherwise noted.) 1ms/div adc reference line transient (v adcref = +1.25v) av dd v adcref 1.25v 3v 10mv/div 500mv/div m ax1329 toc26 1ms/div adc reference line transient (v adcref = +2.04 8 v) av dd v adcref 2.048v 3v 10mv/div 500mv/div m ax1329 toc27 1ms/div adc reference line transient (v adcref = +2.5v) av dd v adcref 2.5v 3v 10mv/div 500mv/div m ax1329 toc28 1ms/div adc reference line transient (v adcref = +1.25v) av dd v adcref 1.25v 5v 20mv/div 500mv/div m ax1329 toc29 1ms/div adc reference line transient (v adcref = +2.04 8 v) av dd v adcref 2.048v 5v 20mv/div 500mv/div m ax1329 toc30
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 17 adc reference supply current vs. analog supply voltage max1329 toc32 av dd supply voltage (v) i avdd ( a) 5.0 4.5 4.0 3.5 3.0 441 442 443 444 445 446 440 2.5 5.5 2.5v 2.048v 1.25v adc reference turn-on time vs. analog supply voltage max1329 toc33 av dd supply voltage (v) turn-on time (ms) 5.0 4.5 4.0 3.5 3.0 2 4 6 8 10 0 2.5 5.5 2.5v 2.048v 1.25v -2.0 -1.0 -1.5 0.5 0 -0.5 1.0 2.0 1.5 0 1000 1500 2000 500 2500 3000 3500 4000 dac integral nonlinearity vs. digital input code (av dd = 3v) max1329 toc34 digital input code inl (lsb) v refdac = 2.5v -2.0 -1.0 -1.5 0.5 0 -0.5 1.0 2.0 1.5 0 1000 1500 2000 500 2500 3000 3500 4000 dac integral nonlinearity vs. digital input code (av dd = 5v) max1329 toc35 digital input code inl (lsb) v refdac = 2.5v -2.0 -1.0 -1.5 0.5 0 -0.5 1.0 2.0 1.5 0 1000 1500 2000 500 2500 3000 3500 4000 dac differential nonlinearity vs. digital input code (av dd = 3v) max1329 toc36 digital input code dnl (lsb) v refdac = 2.5v -2.0 -1.0 -1.5 0.5 0 -0.5 1.0 2.0 1.5 0 1000 1500 2000 500 2500 3000 3500 4000 dac differential nonlinearity vs. digital input code (av dd = 5v) max1329 toc37 digital input code dnl (lsb) v refdac = 2.5v typical operating characteristics (continued) (av dd = 5.0v, v refadc = v refdac = 2.5v for dv dd = 3.0v; t a = +25c, unless otherwise noted.) 1ms/div adc reference line transient (v adcref = +2.5v) av dd v adcref 2.5v 5v 20mv/div 500mv/div m ax1329 toc31 dac supply current vs. analog supply voltage max1329 toc38 av dd (v) i avdd ( a) 5.0 4.5 4.0 3.5 3.0 35 40 45 50 55 60 65 70 75 80 30 2.5 5.5 v refdac = 2.5v, dacb v refdac = 2.5v, daca 1.20 1.60 1.40 2.00 1.80 2.40 2.20 2.60 -40 10 -15 35 60 85 dac offset voltage vs. temperature max1329 toc39 temperature ( c) offset (mv) av dd = 5.5v av dd = 2.7v
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 18 ______________________________________________________________________________________ typical operating characteristics (continued) (av dd = 5.0v, v refadc = v refdac = 2.5v for dv dd = 3.0v; t a = +25c, unless otherwise noted.) op-amp input offset voltage vs. common-mode voltage max1329 toc46 v cm (v) v os (mv) 4.5 4.0 3.0 3.5 1.0 1.5 2.0 2.5 0.5 1 2 3 4 5 6 7 8 9 10 0 0 5.0 av dd = 3v av dd = 5v -1.000 -0.975 -0.950 -0.925 -0.900 -0.875 -0.850 -0.825 -0.800 -40 -15 10 35 60 85 dac gain error vs. temperature max1329 toc40 temperature ( c) error (%) av dd = 5.5v av dd = 2.7v 4 s/div dac slew rate/crosstalk transient response (v refdac = +1.25v) v outa v outb 1mv/div 1v/div 1.25v max1329 toc41 av dd = +5.0v 4 s/div dac slew rate/crosstalk transient response (v refdac = +2.048v) v outa v outb 1mv/div 1v/div 2.048v max1329 toc42 av dd = +5.0v 4 s/div dac slew rate/crosstalk transient response (v refdac = +2.5v) v outa v outb 1mv/div 1v/div 2.5v 0v max1329 toc43 av dd = +5.0v 200ns/div dac digital feedthrough transient response (v refdac = +2.50v) v sclk v outa 20mv/div 2v/div max1329 toc44 av dd = +5.0v op-amp input offset voltage vs. temperature max1329 toc45 temperature (c) v os (mv) 60 35 10 -15 1 2 3 4 5 6 7 8 9 10 0 -40 85 av dd = 5v av dd = 3v v cm = av dd /2
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 19 op-amp psrr vs. frequency max1329 toc48 frequency (khz) psrr (db) 10 100 50 80 70 60 40 30 20 1000 0.01 0.1 1 av dd = 5.0v av dd = 3.0v 500 450 400 350 300 250 200 150 100 50 0 010 1 100 1000 op-amp output impedance vs. frequency max1329 toc49 frequency (khz) impedance ( ? ) op-amp maximum output voltage vs. temperature max1329 toc50 temperature ( c) 60 35 10 -15 10 20 30 40 50 0 -40 85 a b c d e f r l to av dd /2 av dd - v out (ma) a: = r l = 5k ? , av dd = 5v, dv dd = 3v c: = r l = 10k ? , av dd = 5v, dv dd = 3v e: = r l = 100k ? , av dd = 5v, dv dd = 3v b: = r l = 5k ? , av dd = 3v, dv dd = 2v d: = r l = 10k ? , av dd = 3v, dv dd = 2v f: = r l = 100k ? , av dd = 3v, dv dd = 2v max1329 toc51 20 40 60 80 100 120 140 0 a b c d e f r l to avdd/2 op-amp maximum output voltage vs. temperature temperature ( c) 60 35 10 -15 -40 85 r l to av dd /2 av dd - v out (ma) a: = r l = 5k ? , av dd = 5v, dv dd = 3v c: = r l = 10k ? , av dd = 5v, dv dd = 3v e: = r l = 100k ? , av dd = 5v, dv dd = 3v b: = r l = 5k ? , av dd = 3v, dv dd = 2v d: = r l = 10k ? , av dd = 3v, dv dd = 2v f: = r l = 100k ? , av dd = 3v, dv dd = 2v typical operating characteristics (continued) (av dd = 5.0v, v refadc = v refdac = 2.5v for dv dd = 3.0v; t a = +25c, unless otherwise noted.) op-amp supply current vs. analog supply voltage max1329 toc47 av dd (v) i avdd ( a) 5.0 4.5 4.0 3.5 3.0 55 60 65 70 75 80 85 90 95 100 50 2.5 5.5
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 20 ______________________________________________________________________________________ typical operating characteristics (continued) (av dd = 5.0v, v refadc = v refdac = 2.5v for dv dd = 3.0v; t a = +25c, unless otherwise noted.) op-amp gain and phase vs. frequency max1329 toc52 frequency (khz) gain/phase (db/deg) 10 100 -60 -90 -120 -150 60 30 0 -30 -180 1000 0.1 1 av dd = 5v, 3v c l = 0pf, 220pf av dd = 5v c l = 0pf av dd = 3v c l = 0pf av dd = 3v c l = 220pf av dd = 3v c l = 220pf gain phase max1329 toc53 com voltage (v) r on ( ? ) 2.5 2.0 1.5 1.0 0.5 95 100 105 110 115 120 125 130 135 140 90 0 3.0 analog switch on-resistance vs. com voltage (av dd = 3v) t a = +85 c t a = +25 c t a = -40 c analog switch on-resistance vs. com voltage (av dd = 5v) max1329 toc54 com voltage (v) r on ( ? ) 5 4 2 3 85 90 95 100 110 105 115 120 80 16 t a = +85 c t a = +25 c t a = -40 c analog switch turn-on/-off time vs. analog supply voltage max1329 toc55 av dd (v) t on /t off (ns) 5.0 4.5 4.0 3.5 3.0 10 20 30 40 50 60 70 0 2.5 5.5 t on , dv dd = 3v t on , dv dd = 2v t off , dv dd = 2v t off , dv dd = 3v r l = 1k ? analog switch turn-on/-off time vs. temperature max1329 toc56 temperature ( c) t on/ t off (ns) 60 35 -15 10 10 20 30 40 60 50 70 80 0 -40 85 t on , av dd = 5v t on , av dd = 3v t off , av dd = 3v t off , av dd = 5v r l = 1k ? analog switch leakage current vs. temperature max1329 toc57 temperature ( c) i leakage (pa) 60 35 10 -15 20 40 60 80 100 120 140 160 180 200 0 -40 85 off leakage on leakage analog switch on-response vs. frequency max1329 toc58 frequency (khz) gain (db) 110 -2 4 2 0 -4 -6 -8 -10 100 0 0.1 av dd = 5v av dd = 3v analog switch crosstalk and off isolation vs. frequency (av dd = 3v) max1329 toc59 frequency (khz) off isolation (db) 100 1000 -80 -90 -100 -110 -120 -40 -50 -60 -70 -130 10,000 0.1 1 10 off isolation crosstalk analog switch crosstalk and off isolation vs. frequency (av dd = 5v) max1329 toc60 frequency (khz) off isolation (db) 100 1000 -80 -90 -100 -110 -120 -40 -50 -60 -70 -130 10,000 0.1 1 10 off isolation crosstalk
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 21 charge-pump efficiency vs. output current (av dd = 3v) max1329 toc64 i out (ma) efficiency (%) 20 15 10 5 10 20 30 40 50 60 70 80 90 100 0 025 dv dd = 1.8v dv dd = 2.5v dv dd = 3.0v dv dd = 2.0v 0 20 60 40 80 100 -5 35 15 55 75 95 115 temperature-sensor thermal step response (+25 c to +85 c) max1329 toc62 time (s) temperature ( c) = 11s 80 85 90 95 100 105 110 115 120 2.5 3.5 3.0 4.0 4.5 5.0 5.5 internal temperature-sensor supply current vs. supply voltage max1329 toc63 av dd (v) i avdd ( a) internal 2.5v reference clkio = 3.6864mhz adc clock div = 1 conversion rate = 4ksps typical operating characteristics (continued) (av dd = 5.0v, v refadc = v refdac = 2.5v for dv dd = 3.0v; t a = +25c, unless otherwise noted.) temperature-sensor accuracy vs. temperature max1329 toc61 temperature ( c) error ( c) 60 35 10 -15 -1.0 -0.5 0 0.5 1.0 1.5 -1.5 -40 85 internal external charge-pump efficiency vs. output current (av dd = 4v) max1329 toc65 i out (ma) efficiency (%) 20 15 10 5 10 20 30 40 50 60 70 80 90 100 0 0 25 dv dd = 2.2v dv dd = 2.5v dv dd = 3.0v dv dd = 3.6v charge-pump efficiency vs. output current (av dd = 5v) max1329 toc66 i out (ma) efficiency (%) 20 15 10 5 10 20 30 40 50 60 70 80 90 100 0 025 dv dd = 2.7v dv dd = 3.3v dv dd = 3.6v dv dd =3.0v charge-pump output voltage vs. output current (av dd = 3v) max1329 toc67 i out (ma) av dd (v) 45 40 35 30 25 20 15 10 5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 2.5 050 dv dd = 1.8v dv dd = 2.0v dv dd = 3.0v dv dd = 2.5v max1329 toc68 i out (ma) av dd (v) 45 40 35 30 25 20 15 10 5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 3.5 050 charge-pump output voltage vs. output current (av dd = 4v) dv dd = 2.5v dv dd = 2.2v dv dd = 3.6v dv dd = 3.0v
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 22 ______________________________________________________________________________________ typical operating characteristics (continued) (av dd = 5.0v, v refadc = v refdac = 2.5v for dv dd = 3.0v; t a = +25c, unless otherwise noted.) charge-pump output voltage vs. output current (av dd = 5v) max1329 toc69 i out (ma) av dd (v) 45 40 35 30 25 20 15 10 5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 4.5 050 dv dd = 2.7v dv dd = 3.3v dv dd = 3.0v dv dd = 3.6v 200 260 240 220 300 280 380 360 340 320 400 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 charge-pump supply current vs. supply voltage max1329 toc73 dv dd (v) i dvdd ( a) av dd = 3.0v av dd = 4.0v av dd = 5v 2ms/div charge-pump line transient response for +2.0v to +2.5v step input av dd dv dd 2.5v 2v 100mv/div 500mv/div max1329 toc72 av dd = +3.0v , 3.0k ? load 4 s/div charge-pump ripple (i out = 5ma, dv dd = 2v, charge-pump clock = 78khz) av dd 2mv/div max1329 toc70 av dd = +3.0v, dv dd = +2.0v 1ms/div charge-pump load transient response for 0.1ma to 1.0ma load av dd i avdd 1ma 0 1mv/div max1329 toc71 av dd = +3.0v , dv dd = +2.0v
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 23 pin description pin max1329 MAX1330 name function 1 1 dpio1 digital programmable input/output 1 2 2 dpio2 digital programmable input/output 2 3 3 dpio3 digital programmable input/output 3 4 4 dpio4 digital programmable input/output 4 5 5 dout serial-data output. dout outputs serial data from the data register. dout changes on the falling edge of sclk and is valid on the rising edge of sclk. when cs is high, dout is high impedance, unless apio1 is programmed for spi mode. 6 6 sclk serial-clock input. apply an external serial clock to transfer data to and from the device. when cs is high, sclk is inactive unless apio3 is configured for spi mode. then the input on sclk is level-shifted and output at apio3. 77din serial-data input. data on din is clocked in on the rising edge of sclk when cs is low. when cs is high, din is inactive unless apio2 is configured for spi mode. then the input on din is level-shifted and output at apio2. 88 cs active-low chip-select input. drive cs low to transfer data to and from the device. when cs is high and apio4 is configured for spi mode, apio4 is low. 99 rst1 open-drain reset output 1. rst1 remains low while dv dd is below 1.8v. rst1 can be reprogrammed as a push-pull, active-high, or active-low status register interrupt output. 10 10 rst2 open-drain reset output 2. rst2 remains low while dv dd is below 2.7v. rst2 can be reprogrammed as a push-pull, active-high, or active-low status register interrupt output. 11 11 apio1 analog programmable input/output 1 12 12 apio2 analog programmable input/output 2 13 13 apio3 analog programmable input/output 3 14 14 apio4 analog programmable input/output 4 15 15 sno1 analog switch 1 normally-open terminal 16 16 scm1 analog switch 1 common terminal 17 17 snc1 analog switch 1 normally-closed terminal 18 18 in1+ operational amplifier 1 noninverting input 19 19 in1- operational amplifier 1 inverting input. also internally connected to adc mux. 20 20 out1 operational amplifier 1 output. also internally connected to adc mux. 21 n.c. no connection. not internally connected. 22 fbb dacb force-sense feedback input. also internally connected to adc mux. 23 outb dacb force-sense output. also internally connected to adc mux. 21 in2+ operational amplifier 2 noninverting input 22 in2- operational amplifier 2 inverting input. also internally connected to adc mux. 23 out2 operational amplifier 2 output. also internally connected to adc mux.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 24 ______________________________________________________________________________________ pin description (continued) pin max1329 MAX1330 name function 24 24 outa daca force-sense output. also internally connected to adc mux. 25 25 fba daca force-sense feedback input. also internally connected to adc mux. 26 26 refdac dac internal reference buffer output/dac external reference input. in internal reference mode, refdac provides a 1.25v, 2.048v, or 2.5v internal reference buffer output. in external dac reference buffer mode, disable internal reference buffer. bypass refdac to agnd with a 1f capacitor. 27 27 snc2 analog switch 2 normally-closed terminal 28 28 scm2 analog switch 2 common terminal 29 29 sno2 analog switch 2 normally-open terminal 30 30 ain2 analog input 2. also internally connected to adc mux. 31 31 ain1 analog input 1. also internally connected to adc mux. 32 32 refadc adc internal reference buffer output/adc external reference input. in internal reference mode, refadc provides a 1.25v, 2.048v, or 2.5v internal reference buffer output. in external adc reference buffer mode, disable internal reference buffer. bypass refadc to agnd with a 1f capacitor. 33 33 refadj internal reference output/reference buffer amplifiers input. in internal reference mode, bypass refadj to agnd with a 0.01f capacitor. in external reference mode, disable internal reference. 34 34 agnd analog ground 35 35 av dd analog supply input. bypass av dd to agnd with at least a 0.01f capacitor. with the charge pump enabled, see table 32 for required capacitor values. 36 36 c1b charge-pump capacitor input b. connect c fly across c1a and c1b. see table 32 for required capacitor values. 37 37 c1a charge-pump capacitor input a. connect c fly across c1a and c1b. see table 32 for required capacitor values. 38 38 dv dd digital supply input. bypass dv dd to dgnd with at least a 0.01f capacitor. when using charge pump, see table 32 for required capacitor values. 39 39 dgnd digital ground 40 40 clkio clock input/output. in internal clock mode, enable clkio output for external use. in external clock mode, apply a clock signal at clkio for the adc and charge pump. ep exposed pad. the exposed pad is located on the package bottom and is internally connected to agnd. connect ep to the analog ground plane. do not route any pcb traces under the package.
detailed description the max1329/MAX1330 smart dass are based on a 312ksps, 12-bit sar adc with a 1ksps, 16-bit dsp mode. the adc includes a differential multiplexer, a pro- grammable gain amplifier (pga) with gains of 1, 2, 4, and 8, a 20-bit accumulator, internal dither, a 16-word fifo, and an alarm register. the max1329/MAX1330 operate with a digital supply down to 1.8v and feature an internal charge pump to boost the supply voltage for the analog circuitry that requires 2.7v to 5.5v. the max1329/MAX1330 include an internal reference with programmable buffer for the adc, two analog exter- nal inputs as well as inputs from other internal circuitry, an internal/external temperature sensor, internal oscilla- tor, dual single-pole, double-throw (spdt) switches, four digital programmable i/os, four analog programmable i/os, and dual programmable voltage monitors. the max1329 features dual 12-bit force-sense dacs with programmable reference buffer and one opera- tional amplifier. the MAX1330 includes one 12-bit force- sense dac with programmable reference buffer and dual op amps. daca can be sequenced with a 16-word fifo. the dac buffers and op amps have internal ana- log switches between the output and the inverting input. power-on reset after a power-on reset, the dv dd voltage supervisor is enabled with thresholds at 1.8v and 2.7v. all digital and analog programmable i/os (dpios and apios) are configured as inputs with pullups enabled. the internal oscillator is enabled and is output at clkio once the 1.8v reset trip threshold has been exceeded and the subsequent timeout period has expired. see the register bit descriptions section for the default values after a power-on reset. power-on setup after applying power to av dd : 1) write to the reset register. this initializes the tem- perature sensor and voltage reference trim logic. 2) within 3ms following the reset, configure the charge pump as desired by writing to the cp/vm control register. the details of programming the charge pump are described in the charge pump section. charge pump power av dd and dv dd by any one of the following ways: drive av dd and dv dd with a single external power supply, drive av dd and dv dd with separate external power supplies, or drive dv dd with an external supply and enable the internal charge pump to gener- ate av dd or short dv dd to av dd internally. max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 25 t ds t css t dh t dv t do t tr cs sclk din dout t csh t cyc t ch t cl t csh figure 1. detailed serial-interface timing diagram dv dd c load = 20pf 3k ? dout a) for enable, high impedance to v oh and v ol to v oh . for disable, v oh to high impedance. b) for enable, high impedance to v ol and v oh to v ol . for disable, v ol to high impedance. dout 3k ? c load = 20pf figure 2. dout enable and disable time load circuits
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 26 ______________________________________________________________________________________ upon a power-on reset, the charge pump is disabled. enable the charge pump through the cp/vm control register. when the charge pump is in its off state, av dd is isolated from dv dd unless the bypass switch is enabled. to bypass the charge pump and directly con- nect dv dd to av dd , enable (close) the bypass switch through the cp/vm control register (see tables 21 and 22). during the on mode, the charge pump boosts dv dd and regulates the voltage to generate the select- ed output voltage at av dd . the charge-pump output voltage selections are 3.0v, 4.0v, or 5.0v. the charge-pump clock and adc clock are synchro- nized from the same master clock. the charge pump uses a pulse-width-modulation (pwm) scheme to regu- late the output voltage. the charge pump supports a maximum load of 25ma of current to an external device including what is required for internal circuitry. power modes three power modes are available for the max1329/ MAX1330: shutdown, sleep, and normal operation. in shut- down mode, all functional blocks are powered down except the serial interface, data registers, and wake-up circuitry (if enabled). sleep mode is identical to shutdown mode except the dv dd voltage monitors (if enabled) remain active. global sleep or shutdown mode is initiated through a dpio configured as slp or shdn inputs. in normal mode, each analog and digital block can be powered up or shut down individually through its respective control register. voltage supervisors the max1329/MAX1330 provide two programmable volt- age supervisors, one for dv dd and one for av dd . the dv dd voltage supervisor has two thresholds (set to 1.8v and 2.7v by default) that are both enabled after a power- on reset. on initial power-up, rst1 is assigned the 1.8v monitor output and rst2 is assigned the 2.7v monitor output, both for dv dd . if dv dd falls below the 1.8v or 2.7v threshold, the vm1a bit or vm1b bit, respectively, in the status register is set. the vm1a and vm1b status bits can also be mapped to the interrupt generator. the default states of rst1 and rst2 are open-drain outputs but can be programmed as push-pull status register interrupts through the cp/vm control register. the av dd voltage supervisor provides three program- mable thresholds. if av dd falls below the programmed threshold, the vm2 bit is set in the status register. the vm2 status bit can also be mapped to the interrupt generator. interrupt generator the interrupt generator accepts inputs from other internal circuits to provide an interrupt to an external microcontroller (c). the sources for generating an interrupt are program- mable through the serial interface. possible sources include a rising or falling edge on the digital and analog programmable inputs, adc alarms, an adc conversion complete, an adc fifo full, an adc accumulator full, and the voltage-supervisor outputs. the interrupt causes rst1 and/or rst2 to assert when configured as an interrupt out- put. the interrupt remains asserted until the status register is read. see the cp/vm control register for programming the rst1 and rst2 outputs as interrupts and the interrupt mask register for programming the interrupt sources. internal oscillator and programmable clock dividers the max1329/MAX1330 feature an internal oscillator, which operates at a fixed frequency of 3.6864mhz. when enabled, the internal oscillator provides the master clock source for the adc and charge pump. to allow external devices to use the internally generated clock, configure clkio as an output through the clock control register. the clkio output frequency is configurable for 0.9216mhz, 1.8432mhz, and 3.6864mhz. when the inter- nal oscillator is enabled, and regardless of the clkio out- put frequency, the adc and charge-pump clock dividers always receive a 3.6864mhz clock signal (see figure 3). after a power-on reset, clkio defaults to an output with the divider set to 2 (resulting in 1.8432mhz). internal oscillator 4.9152mhz (off, on) clock input divider (off, /1, /2, /4) osce = 0 clock output divider (off, /1, /2, /4) osce = 1 charge-pump clock divider (/32, /64, /128, /256) adc (acquire clks) (adc control) (adc setup) clkio sclk mux osce 0 1 mux charge pump (off, 3v, 4v, 5v) adc clock divider (/1, /2, /4, /8) figure 3. clock-divider block diagram
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 27 for external clock mode, disable the internal oscillator, which then configures clkio as an input. apply an external clock at clkio with a frequency up to 20mhz. the input clock divider can be set to 1, 2, or 4. the out- put of the clkio input divider goes to the input of charge pump and adc clock dividers. note: when using the internally generated clock, enter- ing shutdown or sleep mode causes clkio to become an input. to prevent crowbar current, connect a 500k ? resistor from clkio to dgnd. digital and analog programmable i/os the max1329/MAX1330 provide four digital programma- ble i/os (dpio1Cdpio4) and four analog programmable i/os (apio1Capio4). the dpios and apios can be con- figured as logic inputs or outputs through the dpio and apio control registers. the dpios are powered by dv dd . likewise, the apios are powered by av dd . when configured as inputs, internal pullups can be enabled through the dpio and apio setup registers. digital programmable i/o dpio1Cdpio4 are powered by dv dd and are program- mable as the following: ? general-purpose input ? wake-up input (internal oscillator enable) ? power-down mode (sleep or shutdown) control input ? dac loading or sequencing input ? adc acquisition and conversion control input ? dac, op amp, and spdt switch control input ? adc data-ready output ? general-purpose output analog programmable i/o apio1Capio4 are powered by av dd and are program- mable as the following: ? general-purpose input ? wake-up input (internal oscillator enable) ? general-purpose output ? digital input/output for signals to be level-shifted from/to the spi interface temperature sensor an internal temperature sensor measures the device temperature of the max1329/MAX1330. the adc con- verts the analog measurement from the internal temper- ature sensor to a digital output (see table 1). the temperature measurement resolution is +0.125c for each lsb and the measured temperature can be calcu- lated using the following equation: t = adc output data/8c where adc output data is the decimal value of the twos complement result. the max1329/MAX1330 support external single-ended and differential temperature measurements using a diode connected transistor between ain1 and agnd, ain2 and agnd, or ain1 and ain2. select the appropriate channel for conversion through the adc setup register. voltage references the internal unbuffered 2.5v reference is externally accessible at refadj. separate adc and dac refer- ence buffers are programmable to output 1.25v, 2.048v, or 2.5v refadc and refdac. the reference and buffers can be individually controlled through the adc control and dac control registers. power down the internal reference to apply an external reference at refadj as an input to the adc and dac reference buffers. power down the reference buffers to apply exter- nal references directly at refadc and refdac. note: all temperature sensor measurements use the voltage at refadj as a reference and require a 2.5v ref- erence for accurate results. operational amplifiers the max1329 includes one uncommitted operational amplifier. the MAX1330 includes two op amps. these op amps feature rail-to-rail inputs and outputs, with a bandwidth of 1mhz. the op amps are powered down through the dac control register. an internal analog switch shorts the negative input to the output when enabled through the switch control register or a dpio configured as a switch control input. when powered down, the outputs of the op amps go high impedance. adc output data temperature ( c) two? complement hex +85.000 0010 1010 1000 2a8 +70.000 0010 0011 0000 230 +25.000 0000 1100 1000 0c8 +0.250 0000 0000 0010 002 +0.125 0000 0000 0001 001 0 0000 0000 0000 000 -0.125 1111 1111 1111 fff -0.250 1111 1111 1110 ffe -25.000 1111 0011 1000 f38 -40.000 1110 1100 0000 ec0 table 1. temperature vs. adc output
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 28 ______________________________________________________________________________________ single-pole/double-throw (spdt) switches the max1329/MAX1330 provide two uncommitted spdt switches that can also be configured as a double- pole/single-throw (dpst) switch (see tables 28 and 29). each switch has a typical on-resistance of 115 ? at av dd = 3v. the switch is controlled through the switch control register or a dpio configured to control the switches. analog-to-digital converter (adc) the max1329/MAX1330 include a 12-bit sar adc with a programmable-gain amplifier (pga), input multiplex- er, and digital post-processing. the analog input signal feeds into the differential input multiplexer and then into the pga with gain settings of 1, 2, 4, or 8. the tempera- ture sensor and supply voltage measurements bypass the pga. both unipolar and bipolar transfer functions are selectable. the adc done status bit (add in the status register) can be programmed to provide an interrupt. any of the dpios can be configured as a convst input to directly control the acquisition time and synchronize the conver- sions. a 16-word fifo stores the adc results until the 12-bit data is read by the external c. analog inputs the max1329/MAX1330 provide two external analog inputs: ain1 and ain2. the inputs are rail-to-rail and can be used differentially or single-ended to ground. the analog inputs can also be used for remote temper- ature sensing with external diodes. ain1 and ain2 feed directly into a differential multiplexer. this 16-channel multiplexer is segmented into an upper and a lower multiplexer (see tables 7 and 8 for configu- ration). adc fifo register the adc writes its results in the adc fifo, which stores up to sixteen 16-bit words. each 16-bit word in the fifo includes a 4-bit fifo address and the 12-bit data result from the adc. the adc fifo includes four pointers: depth, interrupt, write, and read configured by writing to the adc fifo register (see figure 4). a depth pointer sets the working depth of the fifo such that locations beyond the depth pointer are inaccessible for writing or reading. the interrupt pointer sets the loca- tion that causes an interrupt every time data has been written to that location. set the interrupt pointer to the same or lower location than the depth pointer. the inter- rupt pointer is set equal to the depth pointer if written with a value greater than the depth pointer. a write to the adc fifo register causes the write and read pointers to reset to location 0. setting the depth pointer to location 0 disables the fifo. every time a conversion completes, the data is written to the present location of the write pointer, which then incre- ments by 1. the write pointer continues to increment until the depth pointer location has been written. the write pointer then moves to location 0 and continues to incre- ment but must remain behind the read pointer. once the last valid fifo location has been written, no further adc results are written to the fifo until the next fifo location is cleared by a read. when the adc fifo is enabled, the read pointer points to location 0. when a read occurs, the pointer then increments by 1 only if 15 of the 16 bits are clocked out successfully. reading the fifo is done in 16-bit words consecutively as long as a serial clock is present. the read pointer must stay one location behind the write pointer. when the write pointer is one location ahead of the read pointer and the read continues, it clocks out the current read location over and over again until the write pointer increments. the fifo can be accessed simultaneously by the serial interface to read a result and by the adc to write a result, but the read and write pointers are never at the same address. adc accumulator, decimation, and dither mode the accumulator is used for oversampling. in this mode, up to 256 samples are accumulated in the adc accumulator register. this is a 24-bit read register with 1 bit for dither enable, 3 bits for the accumulator count, and 20 bits for the accumulated adc conversions. the adc fifo 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 write pointer read pointer depth pointer interrupt pointer figure 4. adc fifo
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 29 accumulator is functional for the normal, fast power- down, and burst modes, but cannot be used for temperature-sensor conversions. the 20-bit binary accumulator provides up to 256 times oversampling and binary digital filtering. the digital filter has a sinc response and the notch locations are deter- mined by the sampling rate and the oversampling ratio (see the applying a digital filter to adc data using the 20-bit accumulator section). there is a digital-signal- processing mode where dither is added to the over- sampling to extend the resolution from 12 to 16 bits. in this mode, a sample rate of 1220sps can be main- tained. the oversampling rate (osr) required to achieve an increase in resolution is osr = 2 2n , where n is the additional bits of resolution. see the adc accumulator register section. adc alarm mode the adc greater-than (gt) and less-than (lt) alarm registers can be used to generate an interrupt once the adc result exceeds the alarm register value. the alarm registers also control the number of alarm trips required and whether or not they need to be consecutive to gen- erate an interrupt. the gt and lt alarms are pro- grammed through the adc gt and lt alarm registers. the alarms are functional for the normal, fast power- down, and burst modes. adc transfer functions figures 5 and 6 provide the adc transfer functions for unipolar and bipolar mode. the digital output code format is binary for unipolar mode and twos comple- ment for bipolar mode. calculate 1 lsb using the following equation: 1 lsb = v refadc /(gain x 4096) for both unipolar and bipolar modes, where v refadc is the reference voltage at refadc and gain is the pga gain. in unipolar mode, the output code ranges from 0 to 4095 for inputs from zero to full- scale. in bipolar mode, the output code ranges from -2048 to +2047 for inputs from negative full-scale to positive full-scale. digital-to-analog converter (dac) the max1329 includes two 12-bit dacs (daca and dacb) and the MAX1330 includes one 12-bit dac (daca). the dacs feature force-sense outputs and daca includes a 16-word fifo. each dac is double- buffered with an input and output register (see figure 7). the daca(b)pd<1:0> bits in the dac control register control the power and write modes for daca and dacb. with the dac(s) powered-up, the three possible com- mands are a write to both the input and output registers, a write to the input register only, or a shift of data from the input register to the output register. with the dac(s) powered-down, only a simultaneous write to both input and output registers is possible. dpio_ can be programmed to shift the input register data to the output register for each dac individually or simultaneously (max1329 only). the value in the output register 0000 0000 0000 0000 0000 0001 0000 0000 0010 4095 4093 input voltage (lsb) binary output code 1111 1111 1101 1111 1111 1110 1111 1111 1111 1 lsb = v refadc (gain x 4096) 0 2 v refadc /gain v refadc /gain 13 1111 1111 1100 0000 0000 0011 full-scale transition figure 5. unipolar transfer function 0+1 -1 1000 0000 0000 1000 0000 0001 1000 0000 0010 +2047 +2045 input voltage (lsb) two's complement output code 0111 1111 1101 0111 1111 1110 0111 1111 1111 0000 0000 0000 0000 0000 0001 1111 1111 1111 1 lsb = v refadc (gain x 4096) -2048 -2046 v refadc (2 x gain) v refadc (2 x gain) v refadc (2 x gain) v refadc (2 x gain) figure 6. bipolar transfer function
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 30 ______________________________________________________________________________________ determines the analog output voltage. an internal switch configures the force-sense output for unity gain config- uration when it is closed. in power-down mode, the dac outputs and feedback inputs are high impedance. daca fifo and direct digital synthesis (dds) logic the daca fifo and dds logic can be used for wave- form synthesis by loading the fifo and configuring the dds mode through the fifoa control register. the fifo is sequenced by writing to the fifo sequence register address or by toggling a dpio configured for this function. the input register value, in conjunction with the fifoa data register values, can be used to create waveforms. the fifoa data register values are added to or sub- tracted from the input register value before shifting to the output register. the fifo data is straight binary (0 to +4095) when the bipolar bit (bipa) is not asserted and as sign magnitude (-2047 to +2047) when bipa is asserted. in sign magnitude mode, the msb represents the sign bit, where 0 indicates a positive number and 1 indicates a negative number. the 11 lsbs provide the magnitude in sign magnitude. the type of waveform generated is determined by the asymmetric/symmetric mode bit (syma), unipolar/bipo- lar mode bit (bipa), and the single/continuous mode bit (cona). all waveforms are generated in phases (see figure 8). for all bit combinations, phase 1 is created by first shifting the input register value to the output reg- ister. for each subsequent sequence, the fifoa data register value is added to the input register before shift- ing to the output register until the programmed fifo depth has been reached (see figure 9a). the fifo depth (dpta<3:0>) can be set to any integer value from 1 to 16 and the fifo always starts at location 1. asserting the syma bit creates phase two by causing the fifo to reverse direction at the end of phase 1 with- out repeating the final value before sequencing back to the beginning (see figure 9c). dac input register dac output register 12-bit dac 16-word dac fifo dds logic fifoa control register from serial i/o from refdac to dac output buffer for daca only figure 7. detailed dac and fifo block diagram fifo location phase 1 phase 2 phase 3 phase 4 dac input register value 16 32 48 64 0 sequence number 0 4 8 12 16 -4 -8 -12 -16 dac input register value plus fifo location 1 value dac input register value minus fifo location 1 value dac input register value minus fifo location 16 value figure 8. dac fifo waveform phases
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 31 0 4 8 12 16 0 326496 16 48 80 112 128 (a) output waveform (unipolar, asymmetric, single) sequence number fifo location 0 4 8 12 16 (b) output waveform (unipolar, asymmetric, continuous) 0 4 8 12 16 (c) output waveform (unipolar, symmetric, single) 0 4 8 12 16 (d) output waveform (unipolar, symmetric, continuous) -16 -8 0 8 16 (e) output waveform (unipolar, asymmetric, single) (f) output waveform (bipolar, asymmetric, continuous) 0 326496 16 48 80 112 128 fifo location 0 326496 16 48 80 112 128 sequence number sequence number fifo location 0 326496 16 48 80 112 128 sequence number fifo location 0 326496 16 48 80 112 128 sequence number fifo location 12 4 -4 -12 0 326496 16 48 80 112 128 sequence number fifo location -16 -8 0 8 16 12 4 -4 -12 (g) output waveform (bipolar, symmetric, single) 0326496 16 48 80 112 128 sequence number fifo location -16 -8 0 8 16 12 4 -4 -12 (h) output waveform (bipolar, symmetric, continuous) 0 326496 16 48 80 112 128 sequence number fifo location -16 -8 0 8 16 12 4 -4 -12 figures 9aC9h. waveform examples using the dac fifo
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 32 ______________________________________________________________________________________ asserting the bipa bit with syma = 1 creates phases three and four (see figure 9g). phases three and four repeat the same sequence as in phases one and two, respectively, but the fifo data is subtracted from the input register data this time through. the final value in phase two is not repeated before proceeding with phase three. the resulting waveform is composed of all four phases. asserting the bipa bit with syma = 0 creates phase four (see figure 9e). phase four repeats the same sequence as in phase one in reverse order, but the fifo data is subtracted from the input register data. in this case, the last location in the fifo is repeated before sequencing back to the beginning. when the cona bit is not asserted, the output is static once the end of the programmed pattern has been reached. asserting the cona bit causes the patterns described above to repeat without repeating the final value (see figures 9b, 9d, 9f, and 9h). the fifo enable bit (ffea) enables the ability to create waveforms. the ffea must be disabled to write to the fifoa data register. any change in the fifoa control register reinitializes the fifo sequencing logic and the next sequence loads the input register value. the daca input and/or output registers can be written directly and not affect the sequencing logic. writing to the daca input register effectively moves the dc offset of the waveform on the next sequence and writing to the daca output register immediately changes the out- put level independent of the fifo. serial interface the max1329/MAX1330 feature a 4-wire serial interface consisting of a chip select ( cs ), serial clock (sclk), data in (din), and data out (dout). cs must be low to allow data to be clocked into or out of the shift register. dout is high-impedance while cs is high, unless apio1 is programmed for spi mode. the data is clocked in at din into the shift register on the rising edge of sclk. data is clocked out at dout on the falling edge of sclk. the serial interface is compatible with spi modes cpol = 0, cpha = 0 and cpol = 1, cpha = 1. a write operation takes effect on the rising edge of sclk used to shift in the lsb (or last bit of the data word being written). if cs goes high before the complete transfer, the write is ignored. cs must be forced high between commands. direct-mode commands the direct-mode commands include the adc convert command and daca and dacb read and write com- mands. the adc convert command is an 8-bit com- mand that initiates an adc conversion, selects the conversion channel through the multiplexer, sets the pga gain, and selects bipolar or unipolar mode. if an adc convert command is issued during a conversion in progress, the current conversion aborts and a new one begins. the mux<3:0>, gain<1:0>, and bip bits settings in the adc setup register are overwritten by the values in the adc convert command. the daca and dacb data write commands set the daca and dacb input and/or output register values, respectively. the daca and dacb data write modes are determined by the dac control register. the daca and dacb data read commands read the daca and dacb input register data, respectively. in register mode, an address byte identifies each regis- ter. the data registers are 8, 16, or 24 bits wide. the adc and daca fifo data registers are variable length up to 256 bits wide. figures 10C17 provide example timing diagrams for various commands. adc conversion timing configure the adc control and setup registers before attempting any conversions. initiate an adc conver- sion with the 8-bit adc convert command (see table 2) or by toggling a dpio input configured for an adc conversion-start function. when a conversion com- pletes, the result is ready to be read in the data regis- ter. in burst mode, the adc data is delivered real time on dout. command name start control adc convert 1 mux<3:0> gain<1:0> bip daca write 0 1 r/ w 0 daca<11:0> dacb write 0 1 r/ w 1 dacb<11:0> register mode* 0 0 r/ w address (adr<4:0>) data (d<255:0>, d<23:0>, d<15:0>, or d<7:0>) table 2. direct-mode definitions * see table 3.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 33 cs sclk din dout x = don? care. 0 0 0 a4a3a2a1a0d n-1 d n -2 d n-3 d n-4 d 2 d 1 d 0 x x figure 10. variable length register-mode data-write operation figure 11. variable length register-mode data-read operation 1m3m2m1 m0 g1 g0 bip x x xx sclk cs din x dout d n-2 d 1 d 0 00100010 xx x d n-1 x = don't care. figure 12. write command to start a normal or fast power-down adc conversion followed by adc data register read cs sclk din dout 0 0 1 a4a3a2a1a0 x x x x x x x x x d n-1 d n-2 d n-3 d n-4 d 2 d 1 d 0 x = don? care.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 34 ______________________________________________________________________________________ d 7 d 6 d 5 d 4 d 2 d 1 d 0 cs sclk din x x dout d 3 d 8 d 9 d 10 d 11 ab 0 1 0 x = don't care. figure 13. write to daca (ab = 0) or dacb (ab = 1). the dac control register programs the write mode. figure 14. read of daca (ab = 0) or dacb (ab = 1) input register xx 001101 xx x sclk din x dout d 23 d 22 d 1 d 0 xx xx 00xx xxxx interrupt asserted reasserts if new interrupt occurs during read rst1/rst2* *rst1 and rst2 are active-high (intp = 1). x = don't care. cs figure 15. read of status register to clear asserted interrupt (rst1/rst2) xxxx xxx cs sclk din x x dout x x x x x ab 1 1 0 d 11 d 10 d 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 x = don't care.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 35 the four conversion modes programmed by the apd<1:0> and auto<2:0> bits in the adc control register are: autoconvert, fast power-down, normal, and burst modes. in normal and fast power-down modes, single conversions are initiated with the adc convert command or by toggling a configured dpio. in fast power-down mode, the pga and adc power down between conversions to reduce power. a minimum of 16 clock cycles is required to complete a conversion in normal or fast power-down mode. burst mode is initiated with one adc convert com- mand and continuously converts on the same channel sending the data directly to dout as long as there is activity on sclk and cs is low. burst mode aborts when cs goes high. in burst mode, sclk directly clocks the adc. for best performance, synchronize sclk with the clkio clock (see figure 18). a mini- mum of 14 clock cycles is required to complete a con- version in burst mode. 010ab d 11 sclk din x d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xxxxxxxx dac dpio previous output new output rising edge triggered x = don't care. cs figure 16. write to daca (ab = 0) or dacb (ab = 1) input register followed by a dpio daca or dacb load d n-1 d 2 d 1 d 0 e n d 2 d 1 sclk din d n dout xxx d 7 d 6 d 5 d 4 d 3 x d n-2 d n-3 d 3 e n-1 e n-2 e n-3 e 3 e 2 e 1 e 0 d 0 apio4 apio3 apio2 e n xxx x e n-1 e n-2 e n-3 apio1 e 3 e 2 e 1 e 0 write to max1329/MAX1330 to enable spi mode write through max1329/MAX1330 to apio device normal write to max1329/MAX1330 set by apio control register set by apio control register set by apio control register set by apio control register inverted cs set to gpo set to gpi set to gpo x = don't care. cs figure 17. write to program and use apio spi mode
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 36 ______________________________________________________________________________________ 1m3m2m1 m0 g1 g0 bip xx x sclk din x dout d 11 d 10 d 0 xxxxxxxx x x d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 x 123 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 45 x x x d 11 track convert track convert adc mode adcdone* *adcdone is an internal signal. rising edge of adcdone sets the add bit in the status register. x = don't care. cs figure 18. write command to start adc burst conversions clocked by sclk with real-time data read (acqck<1:0> = 00, gain<1:0> = 00) 1 m3m2m1 m0 g1 g0 bip sclk din x 123 6 78 45 track convert adc mode adcdone** 12 3 6 78 91011121314151617 45 clkio pd* *pd is an internal signal. when pd is high, the adc is powered-down. **adcdone is an internal signal. rising edge adcdone sets the add bit in the status register. x = don't care. cs figure 19. write command to start adc normal or fast power-down, with autoconvert disabled (auto<2:0> = 000) and conversions clocked by clkio (osce = 0, addiv<1:0> = 00, clkio<1:0> = 11)
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 37 once configured, autoconvert mode initiates with one adc convert command. conversions continue at the rate selected by the adc autoconvert bits (see table 4) until disabled by writing to the adc control register. the autoconvert mode can run only in the normal or fast power-down modes. the autoconvert function must be disabled to use burst mode or dpio convst mode. when writing to the adc control register in fast power- down mode with autoconvert disabled, acquisition begins on the 1st rising adc clock edge after cs tran- sitions high, and ends after the programmed number of clock cycles. the conversion completes a minimum 14 clock cycles after acquisition ends. when autoconvert is enabled, an additional three adc clock cycles are added prior to acquisition to allow the adc to wake up. see figures 19 and 20 for timing diagrams. 1m3m2m1 m0 g1 g0 bip sclk din x 123 678 45 track convert adc mode adcdone** 123 6789101112131819 45 clkio pd* *pd is an internal signal. when pd is high, the adc is powered down. **adcdone is an internal signal. rising edge adcdone sets the add bit in the status register. x = don't care. cs figure 20. write command to start adc normal or fast power-down, with autoconvert enabled and conversions clocked by clkio (osce = 0, addiv<1:0> = 00, clkio<1:0> = 11) clkio adc mode dpio (convst) convert convert edge triggered track track 1 2 3 4 5 6 7 8 9 1011121314151617181920 212223 pd* adcdone** *pd is an internal signal. when pd is high, the adc is powered down. **adcdone is an internal signal. rising edge adcdone sets the add bit in the status register. addiv = 00. figure 21. dpio-controlled adc conversion start
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 38 ______________________________________________________________________________________ see figure 21 for performing an adc conversion using a dpio input programmed as convst. allow at least 600ns for acquisition while the dpio input is low and the acquisition ends on the rising edge of the dpio. the conversion requires an additional 14 adc clock cycles. if the pga gain is set to 4 or 8, the minimum acquisition time is 1.2s due to the increase of the input sampling capacitor. temperature measurement the max1329/MAX1330 perform temperature measure- ment by measuring the voltage across a diode-con- nected transistor at two different current levels. the following equation illustrates the algorithm used for tem- perature calculations: where: v high = sensor-diode voltage with high current flowing (i high ) v low = sensor-diode voltage with low current flowing (i low ) q = charge of electron = 1.602 ? 10 -19 coulombs k = boltzman constant = 1.38 ? 10 -23 j/k n = ideality factor (slightly greater than 1) the temperature measurement process is fully automat- ed in the max1329/MAX1330. all steps are sequenced and executed by the max1329/MAX1330 each time an input channel (or an input channel pair) configured for temperature measurement is scanned. the resulting 12-bit, twos complement number repre- sents the sensor temperature in degrees celsius, with 1 lsb = +0.125c. figure 22 shows the timing for a temperature measurement. an external 2.500v reference can be applied to refadj, provided the internal reference is disabled first. use the temperature correction equation to obtain the correct temperature: t act = 0.997 x t meas - 0.91c use the following equation when using the internal ref- erence: tt t v v act meas meas =+ + ? (.)( . 270 63 1 2 500 r refadj c ) temperature v v x high low = ? ? ? ? ? ? () - q k nxln i i high low temp convert command (sclk, din, dout not shown) there are two adc conversions per temperature conversion. 1 clock = 1/(adc master clock frequency) adc mode track convert track convert start cs stop wait period 93.5 clocks 1st aquisition 90 clocks 2nd aquisition 87 clocks 2nd conversion 17.5 clocks 1st conversion 19 clocks figure 22. temperature-conversion timing
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 39 register name start read/ write (r/ w ) address (adr<4:0>) data (d<255:0>, d<23:0>, d<15:0>, or d<7:0>) adc control 0 0 r/ w 0 0 0 0 0 auto<2:0> apd<1:0> aref<1:0> refe adc setup 0 0 r/ w 0 0 0 0 1 msel mux<3:0> gain<1:0> bip adc data 0 0 1 0 0 0 1 0 adcdata<11:0> xxxx 0 affd<3:0> affi<3:0> adc fifo 0 0 1 00011 affdata<11:0>* affa<3:0>* 0 dith accc<2:0> xxxx adc accumulator 0 0 1 00100 dith accc<2:0> accdata<19:0> adc gt alarm 0 0 r/ w 0 0 1 0 1 gtam gtac<2:0> gtat<11:0> adc lt alarm 0 0 r/ w 0 0 1 1 0 ltam ltac<2:0> ltat<11:0> dac control 0 0 r/ w 0 0 1 1 1 dapd1 dapd0/ oa3e dbpd1 dbpd0/ oa2e oa1e dref<1:0> refe fifoa control 0 0 r/ w 0 1 0 0 0 ffae bipa syma cona dpta<3:0> reserved 0 0 x 0 1 0 0 1 reserved, do not use fifoa data 0 0 r/ w 0 1 0 1 0 ffadata<11:0> xxxx reserved 0 0 x 0 1 0 1 1 reserved, do not use fifo sequence 0 0 w 01100xxxxxxxx clock control 0 0 r/ w 0 1 1 0 1 odly osce clkio<1:0> addiv<1:0> acqck<1:0> cp/vm control 0 0 r/ w 0 1 1 1 0 intp vm1<1:0> vm2cp<2:0> cpdiv<1:0> switch control 0 0 r/ w 01111 dswa/ osw3 dswb osw1 osw2 spdt1<1:0> spdt2<1:0> apio control 0 0 r/ w 1 0 0 0 0 ap4md<1:0> ap3md<1:0> ap2md<1:0> ap1md<1:0> apio setup 0 0 r/ w 1 0 0 0 1 ap4pu ap3pu ap2pu ap1pu ap4ll ap3ll ap2ll ap1ll dp4md<3:0> dp3md<3:0> dpio control 0 0 r/ w 10010 dp2md<3:0> dp1md<3:0> dpio setup 0 0 r/ w 1 0 0 1 1 dp4pu dp3pu dp2pu dp1pu dp4ll dp3ll dp2ll dp1ll vm1a vm1b vm2 add aff acf gta lta apr<4:1> apf<4:1> status 0 0 r 1 0 1 0 0 dpr<4:1> dpf<4:1> mv1a mv1b mv2 madd maff macf mgta mlta mapr<4:1> mapf<4:1> interrupt mask 0 0 r/ w 10101 mdpr<4:1> mdpf<4:1> reserved 0 0 x 1 0 1 1 0 reserved, do not use reserved 0 0 x 1 0 1 1 1 reserved, do not use reserved 0 0 x 1 1 0 0 0 reserved, do not use table 3. register summary note: r/ w = 0 for write, r/ w = 1 for read, x = dont care. * data length can vary from 1 to 16 words, where a word is 16 bits (12 data bits plus 4 address bits). register definitions
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 40 ______________________________________________________________________________________ register name start read/ write (r/ w ) address (adr<4:0>) data (d<255:0>, d<23:0>, d<15:0>, or d<7:0>) reserved 0 0 x 1 1 0 0 1 reserved, do not use reserved 0 0 x 1 1 0 1 0 reserved, do not use reserved 0 0 x 1 1 0 1 1 reserved, do not use reserved 0 0 x 1 1 1 0 0 reserved, do not use reserved 0 0 x 1 1 1 0 1 reserved, do not use reserved 0 0 x 1 1 1 1 0 reserved, do not use reset 0 0 w 11111xxxxxxx x table 3. register summary (continued) note: r/ w = 0 for write, r/ w = 1 for read, x = dont care. * data length can vary from 1 to 16 words, where a word is 16 bits (12 data bits plus 4 address bits). register bit descriptions adc control register the adc control register configures the autoconvert mode, the adc power-down modes, the adc reference buffer, and the internal reference voltage. changes made to the adc control register settings are applied immediately. if changes are made during a conversion in progress, discard the results of that conversion to ensure a valid conversion result. auto<2:0>: adc autoconvert bits (default = 000). the auto<2:0> bits configure the adc to continuously con- vert at the selected interval (see table 4). calculate the conversion rate by dividing the adc master clock fre- quency by the selected number of clock cycles. for example, if the adc master clock frequency is 3.6864mhz and the selected value is 256, the conversion rate is 3.6864mhz/256 or 14.4ksps. the conversion can be started with the adc direct write command and runs continuously using the adc master clock. write 000 to the auto<2:0> bits to disable autoconvert mode. when the autoconvert adc master clock cycle rate is set to 32 and the acquisition time is set to 32 (auto<2:0> = 001, acqck<1:0> = 11, and gain<1:0> = 1x), the acquisi- tion time is automatically reduced to 16 clocks so that the adc throughput is less than the autoconversion interval. the automode operation is unavailable in burst mode. apd<1:0>: adc power-down bits (default = 00). the apd<1:0> bits control the power-down states of the adc and pga (see table 5). when a direct-mode adc conversion command is received, the adc and pga power up except when apd<1:0> = 00. the burst mode outputs data to dout directly in real time as the bit decision is made on the falling edge of sclk and the latest conversion result is also stored in the adc data register. for this mode, the conversion rate is controlled by the sclk frequency, which is limited to 5mhz. if the charge pump is enabled, synchronize sclk with the clkio clock to prevent charge-pump noise from corrupting the adc result. initiate the conver- sion by writing to the adc control register. sclk is required to run continuously during the conversion peri- od. for adc gains of 1 or 2, a total of 14 to 28 clocks (two to 16 for acquisition and 12 for conversion) are required to complete the conversion. for adc gains of 4 or 8, a total of 16 to 44 clocks (four to 32 for acquisition, and 12 for conversion) are required to complete the con- version. bringing cs high aborts burst mode. aref<1:0>: adc reference buffer bits (default = 00). the aref<1:0> bits set the adc reference buffer gain when refe = 0 and the refadc output voltage when refe = 1 (see table 6). set aref<1:0> to 00 to dis- able the adc reference buffer and drive refadc directly with an external reference. refe: internal reference enable bit (default = 0). refe = 1 enables the internal reference and sets refadj to 2.5v. refe = 0 disables the internal reference, allowing an external reference to be applied at refadj, which drives the inputs to the adc and dac reference buffers. the voltage at refadj is also used for temper- ature measurement and must be 2.5v for accurate results. see the temperature sensor section. this bit is mirrored in the dac control register so that writing either location updates both bits. msb lsb name auto2 auto1 auto0 apd1 apd0 aref1 aref0 refe default 00000000
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 41 table 5. adc power-down bit configuration apd1 apd0 adc mode comments 0 0 power-down adc/pga off 0 1 fast power-down adc/pga off between conversions 1 0 normal adc/pga on 1 1 burst adc/pga on, sclk clocks conversion, data clocked out on dout in real time on the falling edge of sclk table 6. adc reference-buffer bit configuration aref1 aref0 adc reference-buffer gain (v/v) (refe = 0) refadc voltage (v) (refe = 1) 0 0 buffer off high-impedance 0 1 0.5 1.25 1 0 0.8192 2.048 1 1 1 2.5 table 4. adc autoconvert bit configuration (auto<2:0>) aut02 auto1 auto0 adc master clock cycles 0 0 0 autoconvert disabled 00 1 32 01 0 64 0 1 1 128 1 0 0 256 1 0 1 512 1 1 0 1024 1 1 1 2048
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 42 ______________________________________________________________________________________ adc setup register the adc setup register configures the input multiplexer, adc gain, and unipolar/bipolar modes to perform a data conversion. changes made to the adc setup register settings are applied immediately. if changes are made during a conversion in progress, discard the results of that conversion to ensure a valid conversion result. msel: multiplexer select bit (default = 0). the msel bit selects the upper or lower multiplexer. msel = 0 selects the upper mux and msel = 1 selects the lower mux. mux<3:0>: multiplexer input select bits (default = 0000). the mux<3:0> bits plus the msel bit select the inputs to the adc (see tables 7 and 8). gain<1:0>: adc gain bits (default = 00). the gain<1:0> bits select the gain of the adc (see table 9). bip: unipolar-/bipolar-mode selection bit (default = 0). for unipolar mode, set bip = 0. for bipolar mode, set bip = 1. for temperature-sensor conversions, use the default gain = 00 and bip = 0. table 7. upper multiplexer bit configuration (msel = 0) positive input negative input mux3 mux2 mux1 mux0 max1329 MAX1330 max1329 MAX1330 0 0 0 0 ain1 agnd 0 0 0 1 ain2 agnd 0 0 1 0 outa agnd 0 0 1 1 fba agnd 0 1 0 0 out1 agnd 0 1 0 1 in1- agnd 0 1 1 0 outb out2 agnd 0 1 1 1 fbb in2- agnd 1 0 0 0 ain1 ain2 1 0 0 1 ain2 ain1 1010 outa fba 1 0 1 1 fba outa 1 1 0 0 out1 in1- 1 1 0 1 in1- out1 1 1 1 0 outb out2 fbb in2- 1 1 1 1 fbb in2- outb out2 msb lsb name msel mux3 mux2 mux1 mux0 gain1 gain0 bip default 00000000
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 43 table 8. lower multiplexer bit configuration (msel = 1) positive input negative input mux3 mux2 mux1 mux0 max1329 MAX1330 max1329 MAX1330 0 0 0 0 ain1 refadc 0 0 0 1 outa refadc 0 0 1 0 out1 refadc 0 0 1 1 outb out2 refadc 0 1 0 0 ain1 refdac 0 1 0 1 outa refdac 0 1 1 0 out1 refdac 0 1 1 1 outb out2 refdac 1000 temp1+ (internal diode anode) temp1- (internal diode cathode) 1001 temp2+ (external diode anode at ain1) temp2- (external diode cathode at ain2) 1010 temp3+ (external diode anode at ain1) agnd 1011 temp4+ (external diode anode at ain2) agnd 1100 dv dd /4 agnd 1101 av dd /4 agnd 1 1 1 0 refadc agnd 1 1 1 1 refdac agnd table 9. adc gain bit configuration gain1 gain0 adc gain setting (v/v) 00 1 01 2 10 4 11 8
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 44 ______________________________________________________________________________________ adc data register the adc data register contains the result from the most recently completed analog-to-digital conversion. the 12-bit result is stored in the adcdata<11:0> bits. the data format is binary for unipolar mode and twos com- plement for bipolar mode. the adc data register con- tents are the same as the adc fifo contents at the last written address, unless writes to the adc fifo have been inhibited. adc fifo register the adc fifo register contents are different for write and read modes. in write mode, the adc fifo register sets the working depth of the fifo and the address that generates an interrupt. in read mode, the adc fifo register holds the adc fifo data and fifo address. write format a serial interface write to the adc fifo register moves the fifo write and read pointers to address 0. affd<3:0>: adc fifo depth bits (default = 0000). affd<3:0> sets the working depth of the fifo (see table 10). if set to a depth of zero, the adc fifo is dis- abled and writes to the aff (adc fifo full) bit in the status register are also disabled. affd<3:0> are write- only bits. affi<3:0>: adc fifo interrupt address bits (default = 0000). affi<3:0> sets the fifo address. after each successful adc conversion, the conversion results are transferred from the adc data register to the fifo location indicated by the fifo write pointer, and the fifo write pointer is incremented. when the fifo write pointer exceeds the value in affi<3:0>, the aff bit in the status register (table 11) is asserted. set the affi<3:0> value equal to or less than the affd<3:0> value. if set to a value greater than affd<3:0>, affi<3:0> is forced to the affd<3:0> value. if affd<3:0> is set to 0000 (depth of zero), the adc fifo is disabled and writes to the aff bit are also dis- abled. affi<3:0> are write-only bits. msb lsb name affd3 affd2 affd1 affd0 affi3 affi2 affi1 affi0 default 00000000 msb name adcdata11 adcdata10 adcdata9 adcdata8 adcdata7 adcdata6 adcdata5 adcdata4 default 00000000 lsb name adcdata3 adcdata2 adcdata1 adcdata0 x x x x default 0000xxxx x = dont care.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 45 table 10. adc fifo depth bit configuration affd3 affd2 affd1 affd0 adc fifo word depth write pointer range 0 0 0 0 fifo disabled 0 0 0 1 2 0-1 0 0 1 0 3 0-2 0 0 1 1 4 0-3 0 1 0 0 5 0-4 0 1 0 1 6 0-5 0 1 1 0 7 0-6 0 1 1 1 8 0-7 1 0 0 0 9 0-8 1 0 0 1 10 0-9 1 0 1 0 11 0-10 1 0 1 1 12 0-11 1 1 0 0 13 0-12 1 1 0 1 14 0-13 1 1 1 0 15 0-14 1 1 1 1 16 0-15 table 11. adc fifo interrupt-address bit configuration affi3 affi2 affi1 affi0 adc fifo interrupt address 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 msb name affdata11 affdata10 affdata9 affdata8 affdata7 affdata6 affdata5 affdata4 default 00000000 lsb name affdata3 affdata2 affdata1 affdata0 affa3 affa2 affa1 affa0 default 00000000 note: data length can vary from 1 to 16 words, where a word is 16 bits (12 data bits plus 4 address bits). read format a single read from the adc fifo register returns the adc fifo data and the 4-bit fifo address (affa<3:0>) corresponding to the location read. after clocking out the 16-bit word, the read pointer increments and continual clock shifts out the 16-bit word at the location pointed to by the adc fifo read pointer. if trying to read from the adc fifo at a location pointed to by the adc fifo write pointer, the fifo repeats the last adc conversion result and correspond- ing adc fifo address equivalent to the adc fifo write pointer. to stop reading, bring cs high after clocking out the 16th bit of a complete word. the read pointer increments after each complete 16-bit word read. it does not increment if the read is aborted by bringing cs high before clocking out all 16 bits. any read operation on the adc fifo register resets the interrupt flag (aff). affdata<11:0>: adc fifo read data bits (default = 0000 0000 0000). affdata<11:0> returns the data written by the adc at the current read pointer location. affa<3:0>: adc fifo read address bits (default = 0000). affa<3:0> returns the address of the current read pointer location. affa<3:0> is never greater than the affd<3:0> programmed value.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 46 ______________________________________________________________________________________ msb name dith accc2 accc1 accc0 accdata19 accdata18 accdata17 accdata16 default 00000000 name accdata15 accdata14 accdata13 accdata12 accdata11 accdata10 accdata9 accdata8 default 00000000 lsb name accdata7 accdata6 accdata5 accdata4 accdata3 accdata2 accdata1 accdata0 default 00000000 read format adc accumulator register the adc accumulator register contains the bits to enable dither, set the accumulator count, and set the 20-bit accumulator data. the dither and accumulator count bits are read/write and the accumulator data is read only. a write to the register resets the accumulator data (accdata<19:0>) to 0x00000 and starts new accumulation. the accdata<19:0> bits remain unchanged until the programmed count of conver- sions is completed. the accumulator is functional for the normal, fast power-down, and burst modes. dith: dither bit (default = 0). when dith = 0, the dither generator is disabled and the accumulator can be used for oversampling and providing digital filtering (see the applying a digital filter to adc data using the 20-bit accumulator section). when dith = 1, the dithering for the adc is enabled. use dithering with the accumulator to oversample data and decimate the result to extend the effective resolution to a maximum of 16 bits and provide digital filtering. accc<2:0> adc accumulator count bits (default = 000). the accc<2:0> bits set the number of adc data conversion results to be accumulated and then written to the accdata register before the acf status bit is set (see table 12). the acf status bit is set in the status register when the data is written to the accdata regis- ter. if the accumulator count is set to 1, the accumulator does not accumulate and the accdata<11:0> is the same as adcdata<11:0> in the adc data register. accdata<19:0>: adc accumulator data bits (default = 0x00000). the accdata<19:0> bits are the summation of up to 256 adc conversion results. when the count set by accc<2:0> has been reached, the acf status bit is set and the accumulated data is written to this register. the data is written to the register at a rate of the adc conversion rate divided by the accumulator count. the accumulator does not exceed 0xfffff. msb lsb name dith accc2 accc1 accc0 xxxx default 0000 xxxx x = dont care. write format table 12. adc accumulator-count bit configuration accc2 accc1 accc0 accumulator count 000 1 001 4 010 8 011 16 100 32 101 64 110 128 111 256
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 47 adc gt alarm register the adc gt alarm register contains the greater-than mode, trip count, and threshold settings. a write to this register address resets the trip counters to zero. the gt alarm is functional for the normal, fast power-down, and burst modes. gtam: adc greater-than alarm mode bit (default = 0). gtam = 0 means that the alarm trips do not need to be consecutive before the gta status bit is set. when gtam = 1, the alarm trips must be consecutive to set the gta status bit. gtac<2:0>: adc greater-than alarm trip count bits (default = 000). gtac<2:0> set the number of conversion results needed to be greater than the alarm threshold before the gta status bit is set (see table 13). gtat<11:0>: adc greater-than alarm threshold bits (default = 0xfff). when the required number of conver- sion results greater than the threshold set by the gtat<11:0> bits have been completed, the gta status bit is set in the status register. clearing the gta status bit by reading the status register or writing to the adc gt alarm register restarts the trip count. the gtat<11:0> bits are in binary format when the adc is in unipolar mode and twos complement format when the adc is in bipolar mode. disable the gt alarm by setting gtat<11:0> to 0xfff when the adc is in unipolar mode and 0x7ff when the adc is in bipolar mode. table 13a. adc greater-than alarm trip count bit configuration gtac2 gtac1 gtac0 number of trips 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 msb name gtam gtac2 gtac1 gtac0 gtat11 gtat10 gtat9 gtat8 default 00001111 lsb name gtat7 gtat6 gtat5 gtat4 gtat3 gtat2 gtat1 gtat0 default 11111111
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 48 ______________________________________________________________________________________ adc lt alarm register the adc lt alarm register contains the less-than mode, trip count, and threshold settings. writing the register address resets the trip counters to zero. the lt alarm is functional for the normal, fast power-down, and burst modes. ltam: adc less-than alarm mode bit (default = 0). ltam = 0 means that the alarm trips need not be con- secutive to cause the lta status bit to be set. ltam = 1 means that the alarm trips must be consecutive before the lta status bit is set. ltac<2:0>: adc less-than alarm trip count bits (default = 000). ltac<2:0> set the number of conver- sion results needed to be less than the alarm threshold before the lta status bit is set. ltat<11:0>: adc less-than alarm threshold bits (default = 0x000). when the required number of adc conversions results less than the threshold set by the ltat<11:0> bits have been completed, the lta status bit is set in the status register. clearing the lta status bit by reading the status register or writing to the adc lt alarm register restarts the trip count. the ltat<11:0> bits are in binary format when the adc is in unipolar mode and twos complement format when the adc is in bipolar mode. disable the lt alarm by setting ltat<11:0> to 0x000 when the adc is in unipolar mode and 0x800 when the adc is in bipolar mode. msb name ltam ltac2 ltac1 ltac0 ltat11 ltat10 ltat9 ltat8 default 00000000 lsb name ltat7 ltat6 ltat5 ltat4 ltat3 ltat2 ltat1 ltat0 default 00000000 table 13b. adc less-than alarm trip count bit configuration ltac2 ltac1 ltac0 number of trips 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 49 dac control register the dac control register configures the power states for daca, dacb, the op amps, dac reference buffer, and the internal reference. the dac control register also controls the daca and dacb input and output register write modes. at power-up, all dacs and op amps are powered down. when powered down, the outputs of the dac buffers and op amps are high impedance. dapd<1:0>: daca power-down bits (default = 00). dapd<1:0> control the power-down states and write modes for daca (see table 14). dbpd<1:0>: (max1329 only) dacb power-down bits (default = 00). dbpd<1:0> control the power-down states and write modes for a dacb write as shown in table 15. oa1e: op amp 1 enable bit (default = 0). set oa1e = 1 to power up op amp 1. oa2e (MAX1330 only): op amp 2 enable bit (default = 0). set oa2e = 1 to power up op amp 2. dref<1:0>: dac reference buffer bits (default = 00). dref<1:0> sets the dac reference buffer gain when refe = 0 (see table 16). dref<1:0> sets the refdac voltage when the refe = 1. refe: internal reference enable bit (default = 0). refe = 1 enables the internal reference and sets refadj to 2.5v. refe = 0 disables the internal reference so an external reference can be applied at refadj, which drives the inputs to the adc and dac reference buffers. this bit is mirrored in the adc control register so that writing either location updates both bits. max1329 msb lsb name dapd1 dapd0 dbpd1 dbpd0 oa1e dref1 dref0 refe default 0 0000000 MAX1330 msb lsb name dapd1 dapd0 x oa2e oa1e dref1 dref0 refe default 0 0x00000 table 14. daca power-down bit configuration dapd1 dapd0 daca power mode daca write mode 0 0 powered down write input and output register 0 1 powered up write input and output register 1 0 powered up write input register 1 1 powered up shift input to output register table 15. dacb power-down bit configuration (max1329 only) dbpd1 dbpd0 dacb power mode dacb write mode 0 0 powered down write input and output register 0 1 powered up write input and output register 1 0 powered up write input register 1 1 powered up shift input to output register
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 50 ______________________________________________________________________________________ fifoa control register the fifoa control register enables the daca fifo, configures the bipolar, symmetry, and continuous modes, and sets the depth of the fifo. any change to the contents of this register resets the fifoa sequence to the starting location. if the fifo operation is enabled (ffae = 1), the next sequence command transfers the daca input register data to the output register. the daca input or output register can be written to when the fifo is enabled without affecting the fifoa sequence, but the daca output and/or input register data is changed. ffae: daca fifo enable bit (default = 0). set ffae = 1 to enable the sequencing function. ffae must be set to 0 to write to the fifo. writes to the fifo when ffae = 1 are ignored. bipa: daca fifo bipolar bit (default = 0). set bipa = 0 to generate a unipolar waveform or set bipa = 1 to gen- erate a bipolar waveform. for a unipolar waveform, the fifoa data is added to the daca input register data during phases 1 and 2 (see figures 8 and 9). for a bipolar waveform, the fifoa data is added to the daca input register data (during phases 1 and 2) and subtracted from the daca input register data (during phases 3 and 4). syma: daca fifo symmetry bit (default = 0). set syma = 0 to generate an asymmetrical waveform, con- sisting of phase 1 (bipa = 0) or phases 1 and 4 (bipa = 1). set syma = 1 to generate symmetry phases 1 and 2 (bipa = 0) or phases 1C4 (bipa = 1). cona: daca fifo continuous bit (default = 0). set cona = 0 to generate a single waveform or set cona = 1 to generate a periodic or continuous waveform. dpta<3:0>: daca fifo depth bits (default = 0000). the dpta<3:0> bits set the depth of the fifoa data register to be used for waveform generation (see table 17). the entire fifoa data register can be filled with 16 words but only the number programmed by dpta<3:0> are used. during waveform generation, the fifoa words are added to the daca input register value before being sent to the daca output register. the first output is the daca input register value. the following value is the daca input register value summed with the fifoa location 1 value. the fifoa locations are incremented until the fifo depth speci- fied by the dpta<3:0> bits has been reached. table 16. dac reference buffer bit configuration dref1 dref0 dac reference buffer gain (v/v) (refe = 0) refdac voltage (v) (refe = 1) 0 0 n/a buffer disabled 0 1 0.5 1.25 1 0 0.8192 2.048 1 1 1.0 2.5 msb lsb name ffae bipa syma cona dpta3 dpta2 dpta1 dpta0 default 00000000
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 51 fifoa data register the fifoa data register stores up to 16 12-bit words that can be used by daca to generate a waveform. ffadata<11:0>: fifoa data bits (default = 0xxxx). ffadata<11:0> represents a 12-bit word that is left justified with 4 dont-care lsbs. a write or read opera- tion always starts at location 1 and ends at the full fifo depth. any attempt to write past the full fifo depth does not overwrite the data just written. any attempt to read past the full fifo depth returns zeroes on dout. a write to the fifoa data register is possible only when the ffae bit in the fifoa control register is 0. if ffae = 1, any write to the fifoa data register is ignored. a read command is possible at any time. if bipa = 0, the data is interpreted as binary (0 to 4095). if bipa = 1, the data is interpreted as sign magnitude (-2047 to +2047). in sign magnitude, the msb represents the sign bit, where 0 indicates a positive number and 1 indicates a negative number. the 11 lsbs provide the magnitude in sign magnitude. table 17. daca fifo depth bit configuration dpta3 dpta2 dpta1 dpta0 fifoa depth 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 msb name ffadata11 ffadata10 ffadata9 ffadata8 ffadata7 ffadata6 ffadata5 ffadata4 default 00000000 lsb name ffadata3 ffadata2 ffadata1 ffadata0 xxxx default 0000 xxxx x = dont care.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 52 ______________________________________________________________________________________ msb lsb name odly osce clkio1 clkio0 addiv1 addiv0 acqck1 acqck0 default 01100001 fifo sequence register a write to the fifo sequence register steps daca to the next fifoa word. a valid write consists of the 8-bit address and 8 bits of data, where the data bits are dont- care bits. the fifo location increments on the 16th rising edge of sclk. successive writes sequence the entire contents of the fifoa data register to the daca output register. the fifo can also be sequenced with the dpios configured as dlda or dlab. the fifo sequence register is a write-only register. clock control register the clock control register enables the internal oscilla- tor and the clkio output, sets the adc acquisition time, and controls the clkio, adc, and charge-pump programmable dividers. odly: oscillator turn-off delay bit (default = 0). set odly = 0 to allow the oscillator to turn off immediately when powered down by the osce bit. if odly = 1, the oscillator turns off 1024 clkio clock cycles after it is powered down by the osce bit. odly also affects dpio sleep mode (slpb). when odly = 1, osce = 1, and clkio<1:0> does not equal 00b, slpb is delayed by 1024 clkio clocks. osce: internal oscillator enable bit (default = 1). set osce = 1 to enable the internal 3.6864mhz oscillator. set osce = 0 to disable the internal oscillator and apply an external oscillator at clkio. when turning off, clkio drives low before becoming an input. do not leave clkio unconnected when configured as an input . the apios and dpios can be configured as a wake-up to set the osce bit. clkio<1:0>: clkio configuration bits (default = 10). clkio<1:0> control the clkio input and output divider settings. see table 18 for the clkio configurations. changes to the clkio<1:0> bits occur on the falling edge of clkio. the odly bit is ignored and has no effect when the clkio is disabled. when osce = 1, changing the clkio output frequency does not change the frequency of the clock to the adc and charge- pump clock dividers. when osce = 0, the output of the clkio input dividers is applied to the adc and charge- pump clock dividers. the changes can take up to four clkio clock cycles due to internal synchronization. addiv<1:0>: adc clock divider bits (default = 00). addiv<1:0> configures the adc clock divider (see table 19), and the output is the adc master clock (figure 3). if osce = 1, the input to the adc clock divider is the output of the 3.6864mhz oscillator. if osce = 0 and clkio<1:0> 00, the output of the clkio input divider is applied to the input of the adc clock divider. acqck<1:0> adc acquisition clock bits (default = 01). acqck<1:0> set the number of adc master clocks used for the adc acquisition (see table 20). for gains of 1 or 2 (gain<1:0> = 0x in the adc control register), the number of acquisition clocks can be set for 2, 4, 8, or 16. for gains of 4 or 8 (gain<1:0> = 1x), the number of acquisition clocks can be programmed to be 4, 8, 16, or 32. table 18. clkio bit configuration clkio1 clkio0 clkio input mode (osce = 0) clkio output mode (mhz) (osce = 1) 0 0 input disabled (output low) 01 f clkio /4 1.2288 10 f clkio /2 2.4567 11 f clkio 4.9152 table 19. adc clock divider bit configuration addiv1 addiv0 adc clock divider 0 0 divide by 1 0 1 divide by 2 1 0 divide by 4 1 1 divide by 8
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 53 cp/vm control register the cp/vm (charge pump/voltage monitor) control register configures the interrupt polarity, charge-pump output voltage settings and power-down, supply volt- age bypass switch state, and the voltage monitor set- tings for dv dd and av dd . intp: interrupt polarity bit (default = 0). intp controls the output polarity for rst1 and rst2 when configured as interrupt outputs. intp = 0 results in active-low oper- ation and intp = 1 selects active-high operation. vm1<1:0>: voltage monitor 1 (vm1) control bits (default = 00). vm1 monitors the voltage on dv dd . the vm1<1:0> bits control the threshold and output settings of vm1 (see table 21). rst1 and rst2 are open-drain outputs when configured as voltage monitor outputs and are push-pull when configured as interrupt outputs. the vm1a status bit is set when dv dd drops below the 1.8v threshold and the vm1b status bit is set when dv dd drops below the 2.7v threshold. vm2cp<2:0>: voltage monitor 2 (vm2) and charge- pump control bits (default = 000). vm2cp<2:0> control the charge pump, the bypass switch, and the av dd volt- age monitor. the charge pump generates a regulated av dd supply voltage from a dv dd input. when activated (vm2cp = 100), the bypass switch internally shorts dv dd to av dd . vm2 monitors the voltage on av dd and sets the vm2 status bit when av dd drops below the threshold. cpdiv<1:0>: charge-pump clock divider bits (default = 00). the cpdiv<1:0> bits set the divider value for the input clock to the charge pump (see table 23). if osce = 1, the input to the charge-pump clock divider is the 3.6864 mhz osc illator output. if osce = 0 and clkio<1:0> 00, the output of the clkio input divider is applied to the input of the charge-pump clock divider. the charge pump is optimized to operate with a clock rate between 39khz and 78khz. set the cpdiv<1:0> and clkio<1:0> bits to provide the optimal clock frequency for the charge pump. table 21. voltage monitor 1 control bit configuration vm11 vm10 rst1 output rst2 output vm1a state (1.8v monitor) vm1b state (2.7v monitor) 0 0 1.8v monitor 2.7v monitor on on 0 1 1.8v monitor interrupt on off 1 0 interrupt 2.7v monitor off on 1 1 interrupt interrupt off off table 20. adc acquisition clock bit configuration adc acquisition clocks acqck1 acqck0 gain = 1, 2 gain = 4, 8 00 2 4 01 4 8 10 8 16 1 1 16 32 msb lsb name intp vm11 vm10 vm2cp2 vm2cp1 vm2cp0 cpdiv1 cpdiv0 default 00000000
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 54 ______________________________________________________________________________________ table 22. voltage monitor 2 and charge-pump control bit configuration vm2cp2 vm2cp1 vm2cp0 charge-pump state bypass switch state vm2 state (threshold voltage) 0 0 0 off open off 0 0 1 on (3v) open on (2.7v) 0 1 0 on (4v) open on (3.8v) 0 1 1 on (5v) open on (4.5v) 1 0 0 off closed off 1 0 1 off open on (2.7v) 1 1 0 off open on (3.6v) 1 1 1 off open on (4.5v) table 23. charge-pump clock divider bit configuration cpdiv1 cpdiv0 charge-pump clock divider 0 0 divide by 32 0 1 divide by 64 1 0 divide by 128 1 1 divide by 256
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 55 max1329 msb lsb name dswa dswb osw1 x spdt11 spdt10 spdt21 spdt20 default 000x0000 MAX1330 msb lsb name dswa x osw1 osw2 spdt11 spdt10 spdt21 spdt20 default 0x000000 x = dont care. switch control register the switch control register controls the two spdt switches and the feedback switches for daca, dacb, op amp 1, and op amp 2. the switches are controlled through the serial interface or by a configured dpio. dswa: daca switch control bit (default = 0). the dswa bit controls the state of the daca switch. a logic-high in dswa or on any dpio_ configured as a daca switch control input causes the daca switch to close. the switch remains open when dswa = 0 and all dpio_ pins configured as daca switch control inputs are logic-low. dpio_ pins not configured as daca switch control inputs are treated as logic zeros. see table 24. dswb (max1329 only): dacb switch control bit (default = 0). a logic-high in dswb or an any dpio_ configured as a dacb switch control input causes the dacb switch to close. the switch remains open when dswb = 0 and all dpio_s configured as dacb switch control inputs are logic-low. dpio_s not configured as dacb switch control inputs are treated as logic zeros. see table 25. osw1: op amp 1 switch control bit (default = 0). the osw1 bit and dpio_ configured in osw1 mode control the state of the op amp 1 switch. if dpio_ is not config- ured for osw1 mode, it is set to 0 as shown in table 26. osw2 (MAX1330 only): op amp 2 switch control bit (default = 0). the osw2 bit and dpio_ configured in osw2 mode control the state of the op amp 2 switch. if dpio_ is not configured for osw2 mode, it is set to 0 as shown in table 27. spdt1<1:0>: single-pole, double-throw switch 1 (spdt1) control bits (default = 00). the spdt1<1:0> bits and dpio_ configured for spdt1 mode control the state of the switch. if dpio_ is not configured for spdt1 mode, it is set to 0 as shown in table 28. spdt2<1:0>: single-pole, double-throw switch 2 (spdt2) control bits (default = 00). the spdt2<1:0> bits and dpio_ configured for spdt2 mode control the state of the switch. if dpio_ is not configured for spdt2 mode, it is set to 0 as shown in table 29. table 24. daca switch control configuration dswa bit dpio4 dpio3 dpio2 dpio1 daca switch state (dswa) 0 0 0 0 0 open x x x x 1 closed x x x 1 x closed x x 1 x x closed x 1 x x x closed 1 x x x x closed x = dont care. table 25. dacb switch control configuration dswb bit dpio4 dpio3 dpio2 dpio1 dacb switch state (dswb) 0 0 0 0 0 open x x x x 1 closed x x x 1 x closed x x 1 x x closed x 1 x x x closed 1 x x x x closed x = dont care.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 56 ______________________________________________________________________________________ table 26. op amp 1 switch control configuration osw1 bit dpio4 dpio3 dpio2 dpio1 op amp 1 switch state (osw1) 0 0 0 0 0 open x x x x 1 closed x x x 1 x closed x x 1 x x closed x 1 x x x closed 1 x x x x closed x = dont care. table 28. spdt1 switch control configuration spdt1 switch state spdt11 bit spdt10 bit dpio4 dpio3 dpio2 dpio1 sno1-to-scm1 state snc1-to-scm1 state 0 0 0000 open open 0 x x x x 1 closed closed 0 x x x 1 x closed closed 0 x x 1 x x closed closed 0 x 1 x x x closed closed 0 1 xxxx closed closed 1 0 0000 open closed 1 x x x x 1 closed open 1 x x x 1 x closed open 1 x x 1 x x closed open 1 x 1 x x x closed open 1 1 xxxx closed open x = dont care. table 27. op amp 2 switch control configuration osw2 bit dpio4 dpio3 dpio2 dpio1 op amp 2 switch state (osw2) 0 0 0 0 0 open x x x x 1 closed x x x 1 x closed x x 1 x x closed x 1 x x x closed 1 x x x x closed x = dont care.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 57 apio control register the analog programmable input/output (apio) control register configures the modes of apio1Capio4. apio1Capio4 i/o logic levels are referenced to av dd and agnd (see analog i/o in the electrical characteristics table). apio_ is configurable as a general-purpose input, active-low wake-up input, general-purpose output, or seri- al-interface, level-shifted buffered i/o. ap_md<1:0>: apio_ mode configuration bits (default = 00). ap_md<1:0> configures the apio_ mode according to table 30. msb lsb name ap4md1 ap4md0 ap3md1 ap3md0 ap2md1 ap2md0 ap1md1 ap1md0 default 00000000 table 29. spdt2 switch control configuration spdt2 switch state spdt21 bit spdt20 bit dpio4 dpio3 dpio2 dpio1 sno2-to-scm2 state snc2-to-scm2 state 0 0 0 0 0 0 open open 0 x xxx1 closed closed 0 x x x 1 x closed closed 0 x x 1 x x closed closed 0 x 1 x x x closed closed 0 1 x x x x closed closed 1 0 0 0 0 0 open closed 1 x xxx1 closed open 1 x x x 1 x closed open 1 x x 1 x x closed open 1 x 1 x x x closed open 1 1 x x x x closed open table 30. apio_ mode bit configuration ap_md1 ap_md0 mode description 0 0 gpi digital input. apio_ logic level read from ap_ll register bit. 0 1 wul digital input. a falling edge on apio_ sets the osce bit to 1 enabling the oscillator. 1 0 gpo digital output. set the apio_ logic level by writing to the ap_ll register bit. 1 1 spi digital input or output. the spi mode functions differ for each apio1Capio4. ? apio1 digital input. dout outputs the apio1 logic level when cs is high, and apio1 is a gpi, when cs is low. set the resistor pullup configuration with the ap1pu bit. ? apio2 digital output. apio2 outputs the din logic level when cs is high and becomes a gpo with the level set by ap2ll bit when cs is low. ? apio3 digital output. apio3 outputs the sclk logic level when cs is high and becomes a gpo with the level set by the ap3ll bit when cs is low. ? apio4 digital output. apio4 inverts and then outputs the cs logic level.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 58 ______________________________________________________________________________________ apio setup register the apio setup register programs the resistor pullup and the logic level for apio1Capio4. ap<4:1>pu: apio resistor pullup bits (default = 1111). ap_pu controls the internal 500k ? (typ) pullup resistor on the corresponding apio_. ap_pu = 0 disables the pullup resistor and ap_pu = 1 connects the pullup resistor to av dd . the pullup resistor is active only when the corresponding apio_ is configured as an input. ap<4:1>ll: apio logic-level bits (default = 0000). if apio_ is programmed as a gpo, set the corresponding ap_ll = 0 to set apio_ to a logic-low level or set ap_ll = 1 to set apio_ to a logic-high level. a read from ap_ll returns the logic level at the corresponding apio_ when the register is read, regardless of the apio mode. dpio control register the digital programmable input/output (dpio) control register programs the modes of the dpio1Cdpio4. dpio1Cdpio4 are referenced to dv dd and dgnd (see digital i/o in the electrical characteristics table). dp_md<3:0>: dpio_ mode configuration bits (default = 0000). dp_md<3:0> configures the corresponding dpio_ (see table 31). dpio setup register the dpio setup register configures the pullup resistor and logic level on dpio1Cdpio4. dp<4:1>pu: dpio resistor pullup bits (default = 1111). dp_pu controls the internal 500k ? (typ) pullup resistor on the corresponding dpio_. dp_pu = 0 disables the pullup resistor and dp_pu = 1 connects the pullup resistor to dv dd . the pullup resistor is active only when the corresponding dpio_ is configured as an input. dp<4:1>ll: dpio logic-level bits (default = 0000). if dpio_ is programmed as a gpo, set the correspond- ing dp_ll = 0 to set dpio_ to a logic-low level or set dp_ll = 1 to set dpio_ to a logic-high level. a read from dp_ll returns the logic level at the corresponding dpio_ when the register is read, regardless of the dpio mode. msb lsb name dp4pu dp3pu dp2pu dp1pu dp4ll dp3ll dp2ll dp1ll default 11110000 msb lsb name ap4pu ap3pu ap2pu ap1pu ap4ll ap3ll ap2ll ap1ll default 11110000 msb name dp4md3 dp4md2 dp4md1 dp4md0 dp3md3 dp3md2 dp3md1 dp3md0 default 00000000 lsb name dp2md3 dp2md2 dp2md1 dp2md0 dp1md3 dp1md2 dp1md1 dp1md0 default 00000000
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 59 table 31. dpio_ mode bit configuration mode d p_ m d 3 d p_ m d 2 d p_ m d 1 d p_ m d 0 max1329 MAX1330 description 0 0 0 0 gpi gpi digital input. dpio_ logic-level read from dp_ll register bit. 0 0 0 1 wul wul digital input. a falling edge on wul sets the osce bit enabling the oscillator. 0 0 1 0 wuh wuh digital input. a rising edge on wuh sets the osce bit enabling the oscillator. 0011 slp slp d i g i tal i np ut. a l og i c- l ow on slp over r i d es the r eg i ster setti ng s and p ow er s d ow n al l ci r cui ts excep t v m 1 and al l the r eg i ster s. a l og i c- hi g h on slp tr ansfer s the p ow er contr ol b ack to the r eg i ster setti ng s. s ee the c l ock c ontr ol reg i ster secti on. 0100 shdn shdn digital input. a logic-low on shdn overrides the register settings and powers down all circuits. a logic-high on shdn transfers the power control back to the register settings. 0 1 0 1 dlab dlab digital input. a rising edge on dlab shifts daca and dacb data from the input register to the output register or sequences through fifoa if enabled. for the MAX1330, this applies only to daca. 0 1 1 0 convst convst digital input. convst controls acquisition time and conversion start. a falling edge on convst puts the adc in acquisition mode. a rising edge on convst starts a single conversion. 0 1 1 1 dlda dlda digital input. a rising edge on dlda shifts daca data from the input to output register or sequences through fifoa if enabled. 1 0 0 0 dswa dswa digital input. dswa and osw3 control the daca and op amp 3 switches, respectively. see the switch control register section. 1 0 0 1 dldb digital input. a rising edge on dldb shifts dacb data from the input to output register. 1 0 1 0 dswb osw2 digital input. dacb and op amp 2 control the dacb and op amp 2 switches, respectively. see the switch control register section. 1 0 1 1 osw1 osw1 digital input. op amp 1 switch control. see the switch control register section. 1 1 0 0 spdt1 spdt1 digital input. spdt1 controls the spdt1 switch. see the switch control register section.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 60 ______________________________________________________________________________________ status register the status register is a 24-bit register that contains status bits from all blocks. setting a status bit causes the interrupt output to assert when the corresponding interrupt mask bit in the interrupt mask register is cleared. if a status bit is set and an event occurs to set it again, the status bit and interrupt output remain asserted. all status bits clear once the status register has been read successfully. updating of the status reg- ister is delayed during a read until the status register read has been completed. vm1a: 1.8v dv dd voltage-monitor status bit (default = 0). vm1a indicates the status of the 1.8v dv dd voltage monitor. the vm1a = 1 when the dv dd voltage drops below the 1.8v threshold. the vm1a bit clears to 0 when the status register is read and only if the condi- tion is no longer true. when the 1.8v dv dd voltage monitor is powered down, the previous state of the bit is maintained until it is read and it cannot be set to 1 in this state. note: the default state is 0. however, at power-up, the voltage monitor asserts vm1a. read the status register after power-up to reset vm1a to 0. vm1b: 2.7v dv dd voltage-monitor status bit (default = 0). vm1b indicates the status of the 2.7v dv dd voltage monitor. vm1b = 1 when the dv dd voltage drops below the 2.7v threshold. the vm1b bit clears to 0 when the status register is read and only if the condition is no longer true. when the 2.7v dv dd voltage monitor is pow- ered down, the previous state of the bit is maintained until it is read and it cannot be set to 1 in this state. note: the default state is 0. however, at power-up, the voltage monitor asserts vm1b. read the status register after power-up to reset vm1b to 0. vm2: av dd voltage-monitor status bit (default = 0). vm2 indicates the status of the av dd voltage monitor. vm2 = 1 when the av dd voltage drops below the threshold programmed by the vm2cp<2:0> bits. vm2 clears to 0 when the status register is read and only if the condition is no longer true. when the av dd voltage monitor is powered down, the previous state of the bit is maintained until it is read and it cannot be set to 1 in this state. add: adc done status bit (default = 0). the add bit indicates when an adc conversion has completed and the data is ready to be read from the adc data regis- ter. add is set to 1 after the data from an adc conver- sion has been written to the adc data register. add clears to 0 when the status register or the adc data register is read. aff: adc fifo full status bit (default = 0). the aff bit indicates that the adc has written data to the adc fifo address programmed by the affi<3:0> bits. the aff bit is set to 1 when the address has been written. aff clears to 0 when the status register is read or when the adc fifo register is read (any number of adc data words) or written. acf: adc accumulator full status bit (default = 0). the acf bit indicates that the programmed number of adc conversion results have been accumulated. the result is saved in the accdata<19:0> bits in the adc accumulator register for the next programmed number of accumulations before it is overwritten. the acf bit sets to 1 when the adc accumulator is filled to the pro- grammed address. the acf bit clears to 0 when the status register is read or when the adc accumulator register is read or written. table 31. dpio_ mode bit configuration (continued) mode d p_ m d 3 d p_ m d 2 d p_ m d 1 d p_ m d 0 max1329 MAX1330 description 1 1 0 1 spdt2 spdt2 digital input. spdt2 controls the spdt2 switch. see the switch control register section. 1 1 1 0 drdy drdy digital output. drdy goes high when a conversion is complete and valid adc data is available in the adc data register. if the adc data or status register is read, drdy returns low. if high, drdy pulses low for one adc master clock cycle while updating the adc data register before returning high. 1 1 1 1 gpo gpo digital output. write to the dp_ll register bits to set the gpo level.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 61 msb name vm1a vm1b vm2 add aff acf gta lta default 0*0*000000 name apr4 apr3 apr2 apr1 apf4 apf3 apf2 apf1 default 00000000 lsb name dpr4 dpr3 dpr2 dpr1 dpf4 dpf3 dpf2 dpf1 default 00000000 * the default states for vm1a and vm1b are 0. however, at power-up, the voltage monitor asserts vm1a and vm1b. gta: adc greater-than (gt) alarm status bit (default = 0). gta = 1 indicates that adc gt alarm has been tripped. the gta bit clears to 0 by reading the status register or by writing the adc gt alarm register. lta: adc less-than (lt) alarm status bit (default = 0). lta = 1 indicates that the adc lt alarm has been tripped. the lta bit clears to 0 by reading the status register or by writing the adc lt alarm register. apr<4:1>: apio rising-edge status bit (default = 0). a logic-high in the apr<4:1> bits indicate that a rising edge has been detected on the corresponding apio_. apr_ clears to 0 when the status register is read. apf<4:1>: apio falling-edge status bit (default = 0). a logic-high in the apf<4:1> bits indicate that a falling edge has been detected on the corresponding apio_. apf_ clears to 0 when the status register is read. dpr<4:1>: dpio rising-edge status bit (default = 0). a logic-high in the dpr<4:1> bits indicate that a rising edge has been detected on the corresponding dpio_. dpr_ clears to 0 when the status register is read. dpf<4:1>: dpio falling-edge status bit (default = 0). a logic-high in the dpf<4:1> bits indicate that a falling edge has been detected on the corresponding dpio_. dpf_ clears to 0 when the status register is read.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 62 ______________________________________________________________________________________ interrupt mask register the interrupt mask register bits enable the status bits to generate an interrupt on rst1 and/or rst2 if pro- grammed as interrupts (configured by vm1<1:0> in the cp/vm control register). clearing a mask bit to 0 enables the corresponding bit in the status register to generate an interrupt. setting a mask bit to 1 prevents the status bit from generating an interrupt. if the inter- rupt output is asserted and another interrupt occurs, the interrupt output remains asserted. interrupt condi- tions on rst1 and/or rst2 are released after recogniz- ing a read to the status register. updating of the status register is delayed until after the status register has been read. if the status register read was aborted or if a new unmasked status bit is set during the read, the interrupt output reasserts at the end of the read (see figure 15). mv1a: 1.8v dv dd voltage-monitor mask bit (default = 1). set mv1a = 0 to unmask the vm1a status bit to generate an interrupt. mv1b: 2.7v dv dd voltage-monitor mask bit (default = 1). set mv1b = 0 to unmask the vm1b status bit to generate an interrupt. mvm2: av dd voltage-monitor mask bit (default = 1). set mvm2 = 0 to unmask the vm2 status bit to gener- ate an interrupt. madd: adc done mask bit (default = 1). set madd = 0 to unmask the add status bit to generate an interrupt. maff: adc fifo full mask bit (default = 1). set maff = 0 to unmask the aff status bit to generate an interrupt. macf: adc accumulator full mask bit (default = 1). set macf = 0 to unmask the macf status bit to gener- ate an interrupt. mgta: adc gt alarm mask bit (default = 1). set mgta = 0 to unmask the gta status bit to generate an interrupt. mlta: adc lt alarm mask bit (default = 1). set mlta = 0 to unmask the lta status bit to generate an interrupt. mapr<4:1>: apio rising-edge mask bits (default = 1111). set mapr_ = 0 to unmask the corresponding apio_ status bit to generate an interrupt. mapf<4:1>: apio falling-edge mask bits (default = 1111). set mapf_ = 0 to unmask the corresponding apio_ status bit to generate an interrupt. mdpr<4:1>: dpio rising-edge mask bits (default = 1111). set mdpr_ = 0 to unmask the corresponding dpio_ status bit to generate an interrupt. mdpf<4:1>: dpio falling-edge mask bits (default = 1111). set mdpf_ = 0 to unmask the corresponding dpio_ status bit to generate an interrupt. reset register a write to the reset register resets all registers to their default values. a valid write consists of the 8-bit address and 8 dont-care bits of data. the reset occurs on the 16th rising edge of sclk. msb name mv1a mv1b mvm2 madd maff macf mgta mlta default 11111111 name mapr4 mapr3 mapr2 mapr1 mapf4 mapf3 mapf2 mapf1 default 11111111 lsb name mdpr4 mdpr3 mdpr2 mdpr1 mdpf4 mdpf3 mdpf2 mdpf1 default 11111111
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 63 applications information power-supply considerations the circuit in figure 23 applies an external 3.0v power supply to both dv dd and av dd . to drive av dd directly, disable the internal charge pump through the cp/vm control register. the bypass switch between dv dd and av dd can be either open or closed in this configuration. figure 24 shows the charge pump enabled to supply av dd . the charge-pump output voltage is set to 5.0v through the cp/vm control register. see the charge- pump component selection section. figure 25 shows dv dd is powered from a battery with the charge-pump output set to 3.0v. the charge pump can draw high peak currents from dv dd under maxi- mum load. select an appropriately sized bypass capac- itor for dv dd ( 10 times c fly ). supply ripple can be reduced by increasing ca vdd and/or the charge-pump clock frequency. running directly off batteries the max1329/MAX1330 can be powered directly from two alkaline cells, two silver oxide button cells, or a lithi- um-coin cell. dv dd requires 1.8v to 3.6v and av dd requires 2.7v to 5.5v for proper operation. save power by running dv dd directly off the battery and shorting to av dd by closing the internal bypass switch. use the 2.7v av dd voltage monitor to detect when it drops to 2.7v. power is saved during this time because the inter- nal charge pump is off. once the battery voltage drops to 2.7v, open the bypass switch and enable the internal charge pump as long as dv dd is between 1.8v and 2.7v. following this procedure optimizes the battery life. digital-interface connections figure 26 provides standard digital-interface connections between the max1329/MAX1330 and a c. the c gen- erates its own 32khz clock for timekeeping and the max1329/MAX1330 provide the high-frequency clock required by the c. see the clock control register sec- tion to program the clkio output and frequency and set the odly bit to delay the turn-off time to enable the c time to go to sleep. during sleep, clkio becomes an input and requires a weak pulldown resistor ( 1m ? ) to minimize power dissipation. see the dpio setup and dpio control registers to program dpio1Cdpio4 as wake-ups. upon wake-up, the internal oscillator starts and outputs to clkio. see the cp/vm control register sec- tion to program the rst1 and rst2 as a reset or interrupt. max1329 MAX1330 dv dd c1a c1b av dd dgnd agnd interrupt v dd dgnd power supply 0.1 f 0.1 f 0.1 f 2.7v to 3.6v c rst1 rst2 reset figure 23. power-supply circuit using an external 3.0v power supply for dv dd and av dd max1329 MAX1330 dv dd rst1 c1a c1b av dd dgnd agnd interrupt v dd dgnd power supply 0.1 f 2.7v to 3.6v c fly 5.0v c avdd c dvdd c rst2 reset figure 24. power-supply circuit using an external 3.0v power supply for dv dd and internal charge pump set to 5v for av dd max1329 MAX1330 dv dd c1a c1b av dd dgnd agnd interrupt v dd dgnd 0.1 f 1.8v to 3.6v c fly 3.0v c avdd c dvdd c e1 rst1 rst2 reset figure 25. power-supply circuit using a battery for dv dd and internal charge pump set to 3.0v for av dd
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 64 ______________________________________________________________________________________ communication with a peripheral device powered by the max1329/MAX1330 the circuit in figure 27 shows the max1329/MAX1330 providing an interface between a c and a peripheral device powered by different supply voltages. this elimi- nates the need for external level-translation circuitry due to the different supply voltages. the internal charge pump boosts the c supply voltage (dv dd ) to the periph- eral device supply voltage (av dd ). see the apio control and apio setup registers to program apio2Capio4 as din, sclk, and cs outputs to the peripheral device, respectively, and apio1 as the dout input from the peripheral device. the digital inputs at din, sclk, and cs are level-translated from dv dd to av dd and output at the configured apio2, apio3, and apio4 outputs. the digital output at dout is level-translated from av dd to dv dd from the configured apio1 input. c dpio2 output sck sclk mosi din miso dout interrupt dpio1 hclkin clkio 32.768khz xout xin interrupt interrupt max1329 MAX1330 rst1 cs rst2 reset figure 26. digital-interface connections c apio4 output sck sclk mosi din miso dout apio3 apio2 apio1 peripheral device din dout sclk agnd dgnd av dd dv dd agnd dgnd dv dd av dd c1a c1b c fly external 1.8v to 3.6v 3.0v/4.0v/5.0v power supply c avdd c dvdd max1329 MAX1330 cs cs figure 27. communication with a peripheral device powered by the max1329/MAX1330
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 65 optical reflectometry application with dual led and single photodiode figure 28 illustrates the max1329 in an optical reflectom- etry application with two transmitting leds and one receiving photodiode. the leds transmit light at specific frequencies onto the sample strip and the photodiode receives the reflections from the strip. set the daca out- put to provide the appropriate bias currents for the leds. the dswa and dswb switches are open in this configu- ration. the led bias current is calculated as i led = v outa /r b . refadc is used as an analog ground and dacb is set to ensure that the photodiode is not forward biased. the i f current is converted to a voltage through the r f resistor and measured by the internal adc. spdt1 and spdt2 are configured as singl e-pole double-throw switches and enable switching between v bat photo diode r f i f q 1 daca outa fba dacb outb fbb sno1 snc1 scm1 refadc refdac refadj 2.5v ref a v = 0.5, 0.82, 1 refdac refdac snc2 sno2 scm2 v bat r b q 2 led led 1.25v 2.50v a v = 0.5, 0.82, 1 dswa dswb spdt1 spdt2 1 f 0.01 f 1 f max1329 figure 28. optical reflectometry application with dual led and single photodiode
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 66 ______________________________________________________________________________________ the two leds. the leds can be powered directly from v bat or from av dd powered by the internal charge pump if the v d of the leds require a higher or regulat- ed voltage. ambient light rejection is performed in the digital domain in this configuration by digitizing the photodiode current with the internal adc while both leds are off and subtracting this from the result when the leds are turned on. three-electrode potentiostat with software-switchable single- or dual- channel connection the max1329 is used in a software switchable single- or dual-channel three-electrode potentiostat application (see figure 29). in both configurations, the dac buffer feedback switches, dswa and dswb, are normally open but can be closed during high sensor current to keep the dac buffer outputs compliant. in the dual- channel configuration, the spdt1 switch is open and the osw1 switch is closed. daca biases the working electrode (we) and dacb biases the reference elec- trode (re) both relative to the counter electrode (ce). the ce is shared by the two channels. in this configura- tion, re is really a second working electrode and i a and i b are the two sensor currents being measured. i a and i b are converted to voltages through r a and r b and measured by the internal adc. in the single-chan- nel configuration, the spdt1 switch is closed and the osw1 switch is open. daca biases the we relative to the re and the re is set by in1-. op amp 1s force- sense configuration holds re constant while the ce swings up and down depending on the sensor current and the sensor impedance. in this configuration, i a is the sensor current being measured. the r 1 resistor is typically a large value to keep op amp 1 stable when the sensor is not present or not active. two-electrode potentiostat with ac and dc excitation the circuit in figure 30 shows the MAX1330 in a two- electrode potentiostat application with both ac and dc excitation to the sensor. the dswa can be open or closed and osw1 and osw2 should be normally open although osw1 can be closed during high sensor current to keep op amp 1 in compliance. refadc is analog ground and the working electrode (we) is con- nected to analog ground through op amp 1. the sensor current to be measured is converted to a voltage through r f and measured by the internal adc. for dc operation, the bias voltage between we and the counter electrode (ce) is set by daca. for ac opera- tion, daca is configured to generate a waveform by programming the fifoa control and fifoa data regis- ters for the desired operation. op amp 2 is configured as a 2nd-order sallen key lowpass filter to smooth the steps in the ac waveform going to the sensor. the daca can be sequenced to create an ac waveform through the spi interface or by configuring one of the dpios and driving it with a clock. the internal adc includes a 16-word fifo to facilitate data gathering during this mode of operation. temperature measurement with two remote sensors for external measurements, select single-ended ain1 and ain2 temperature measurement relative to agnd in the lower multiplexer. two diode-connected 2n3904 transistors are used as external temperature sensing diodes in figure 31. for internal temperature sensor measurements, select internal temperature measure- ment in the lower multiplexer. during all temperature measurements, autoconvert and burst modes are unavailable. divide the adc result by eight to obtain the measured temperature. when using an external reference at refadj, disable the internal reference and use the temperature correction equation in the temperature measurement section.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 67 daca outa fba refadc refdac refadj 2.5v ref a v = 0.5, 0.82, 1 refdac 1.25v 2.50v a v = 0.5, 0.82, 1 dswa 1 f 0.01 f 1 f max1329 dacb refdac i b i a r a outb fbb dswb r b we re ce sno1 snc1 scm1 in1- osw1 out1 r 1 oa1 in1+ spdt1 figure 29. three-electrode potentiostat software-switchable single- or dual-channel connection
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 68 ______________________________________________________________________________________ daca outa refdac fba dswa MAX1330 we ce in1- osw1 out1 oa1 in1+ refadc refdac refadj 2.5v ref a v = 0.5, 0.82, 1 a v = 0.5, 0.82, 1 1 f 0.1 f 1 f osw2 in2+ oa2 r 1 c2 r 2 c1 r 3 out2 in2- 2.50v sensor 1.25v r f figure 30. two-electrode potentiostat with ac and dc excitation
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 69 ain1 agnd 2n3904 mux refadc pga ain1 ain2 out1 outb/out2 fbb/in2- in1- dv dd /4 refadc refdac outa/out3 fba/in3- adc fifo dither accumulator 12-bit adc a v = 1, 2, 4, 8 alarm mux refadj refadc 2.5v ref a v = 0.5, 0.82, 1 ain2 agnd 2n3904 refdac temp sensor temp1 a v = 0.5, 0.82, 1 *for best results, limit c ain1 and c ain2 to 10pf. av dd /4 temp1 agnd c ain1 * temp2 temp3 c ain2 * 1 f 0.01 f 1 f max1329 MAX1330 figure 31. temperature measurement with two remote sensors programmable-gain instrumentation amplifier two op amps and two spdt switches are configured as a programmable-gain instrumentation amplifier in figure 32. it includes a differential input and a single- ended output. spdt1 and spdt2 are configured as single-pole, double-throw switches. the gain is set by the following equations: for switch position 1, and for switch position 2. v r rr vv out in in = + + ? ? ? ? ? ? ? + ? 3 12 1( ) v rr r vv out in in = + + ? ? ? ? ? ? ? + ? 23 1 1( )
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 70 ______________________________________________________________________________________ synthesizing a sine wave the max1329/MAX1330 can easily create up to a 64-point single or periodic sine wave using the daca and fifoa. the 16-word fifo or memory is used to create the first quarter of the waveform and symmetry is used to extend the waveform to produce a complete period. see the dac fifo and direct digital synthesis (dds) logic section for detailed waveform generation. the first data point is the daca input register data. the fifoa data is offset from this initial data. to determine the values to be written to the fifoa data register use the following equation. fifoa_data(n) = a x sin((n/n) x 90) where n = 1 to n, n = dpta<3:0>, a = (v peak /v refdac ) x 4096, v peak is the desired peak voltage of the sine wave, and v refdac is the dac reference voltage pro- grammed at refdac. round the fifoa_data(n) values to the nearest inte- ger and write these values to the fifoa data register. figure 33 shows a sine wave with a 2v p-p output and with a 1.25v offset. write the dac control register with 0x43 to enable daca, enable the internal reference, and to set refdac to 2.5v. write to the daca input and output register by performing a direct mode write with 0x4800 to set daca to midscale or 1.25v. write the fifoa control register with 0x7f to disable fifoa and allow a write to the fifoa data register, enabling bipolar, symmetry, and continuous modes, and setting the depth to 16. the fifoa data calculated from the above equation is 161, 320, 476, 627, 772, 910, 1039, 1159, 1267, 1362, 1445, 1514, 1568, 1607, 1631, and 1638 decimal. write the fifoa data register with 0x0a10 1400 1dc0 2730 3040 38e0 40f0 4870 4f30 5520 5a50 5ea0 6200 6470 65f0 6660 as a contiguous bit stream to fill the fifoa data register with data. write to the fifoa control register with 0xff to enable fifoa and to disal- low writes to the fifoa data register. write to the dpio control register with 0x0007 to program dpio1 as an input to sequence the daca fifo on each rising edge. write to the switch control register with 0x80 to close the daca switch to put the buffer into unity gain. input a continuous clock to dpio1 that is 4 x n times (n = 16) the desired frequency of the synthesized waveform. figure 33 should be observable on outa. MAX1330 r 3 r 2 r 2 r 3 r 1 r 1 in1+ in1- scm1 v out scm2 out1 sno1 snc1 sno2 snc2 v in+ v in- out2 in2+ in2- oa1 osw1 spdt1 oa2 osw2 spdt2 figure 32. programmable-gain instrumentation amplifier, switch position 1 0 0.75 0.50 0.25 1.25 1.00 2.25 2.00 1.75 1.50 2.50 0 10203040506070 sine wave dac sequences dac output (v) figure 33. example sine-wave output
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 71 charge-pump component selection optimize the charge-pump circuit for size, quiescent current, and output ripple by properly selecting the operating frequency and capacitors c dvdd , c fly , and c avdd (table 32). the charge pump is capable of pro- viding a maximum of 25ma including what is used internally. if less than 25ma is required, smaller capaci- tor values can be utilized. for lowest ripple, select 117khz operation (cpdiv<1:0> = 00 and osce = 1 when using the internal oscillator). in addition, increasing c avdd relative to c fly further reduces ripple. for highest efficiency, select 14.6khz operation (cpdiv<1:0> = 11 and osce = 1 when using the internal oscillator) and select the largest practical values for c avdd and c fly while maintaining at least a 30-to-1 ratio. for smallest size, select 117khz operation. see table 32 for some suggested values and resulting ripple for 25ma load current. see figure 34 for load cur- rent vs. flying capacitor value when optimizing for other load currents. note that the capacitors must have low esr to main- tain low ripple. the c fly flying capacitor esr needs to be < 0.1 ? ; and the c avdd and c dvdd filter capaci- tor esr needs to be < 0.3 ? . the c fly flying capacitor can easily be a ceramic capacitor; and the c avdd and c dvdd filter capacitor can be a low-esr tantalum or may need to be a combination of a small ceramic and a larger tantalum capacitor. when dv dd is lower than av dd , the charge pump always operates in voltage-doubler mode. it regulates the output voltage using a pulse-width-modulation (pwm) scheme. using a pwm scheme ensures that the charge pump is synchronous with the internal adc preventing corruption of the conversion results. operating the analog switches the max1329/MAX1330 include two single-pole double- throw (spdt) and three single-pole single-throw (spst) analog switches. the two spdt analog switches are uncommitted and the three spst analog switches are connected between the dac buffer or op amp outputs and the inverting inputs. the analog switches can be controlled using the switch control register or any of the dpios. see the dpio control and dpio setup registers to program the dpios. the dpios should be used when direct control is critical such as synchronizing with another event or if the spi bus bandwidth is not sufficient for the intended application. the register bit for the analog switch is log- ically ord with dpios enabled to control that switch. the spdt1 and spdt2 analog switches can be operat- ed as a spdt or as a double-pole single-throw (dpst). in the dpst mode, both switches can be opened or closed together. this is useful when connecting two external nodes to a common point. if a lower on-resis- tance is required, no_ and nc_ can be connected together externally and be used as a spst analog switch with half the on-resistance. the spst analog switches are intended to be used to set the dac buffers and op amps to unity gain internal- ly by software control. when the dac buffers and op amps are used as transimpedance amplifiers, the spst analog switches can be used to short the external tran- simpedance resistor during high current periods to keep the amplifier output in compliance. charge-pump clock (khz) i load, max (ma) c fly (?) c avdd (?) c dvdd (?) ripple (mv) 25 1.7 55.6 17.4 14.4 12.5 0.9 27.8 8.7 32 25 0.9 27.8 8.7 28.8 12.5 0.4 13.9 4.3 32 25 0.4 13.9 4.3 57.6 12.5 0.2 6.9 2.2 32 25 0.2 6.9 2.2 115.2 12.5 0.1 3.5 1.1 32 table 32. external component selection for 25ma output current and 2v dvdd - v avdd 0.4v (figure 25) charge-pump load current vs. flying capacitor value max1329 fig34 c fly ( f) i load (ma) 4.5 4.0 3.0 3.5 1.0 1.5 2.0 2.5 0.5 5 10 15 20 25 30 35 40 45 50 0 05.0 f cp = 115.2khz f cp = 57.6khz f cp = 14.4khz f cp = 28.8khz figure 34. load current vs. cfly value for 2v dvdd - v avdd 0.4v
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 72 ______________________________________________________________________________________ using the internal reference and reference buffers the max1329/MAX1330 include a precision 2.5v internal reference and two independent programmable buffers for the adc and dacs. see the adc control and dac control registers to enable the internal reference and pro- gram the buffers. the refadj output is fixed at 2.5v (refe = 1) and the refadc and refdac connect to the internal adc reference input and the internal dac refer- ence inputs, respectively. these buffers can be pro- grammed to output 1.25v, 2.048v, or 2.5v independent of each other. this allows the dynamic range of the adc and dacs to be optimized or set differently. this is useful if one of the reference voltages is needed to be approxi- mately av dd /2 to be used as an analog ground. the flexibility of the reference circuit allows the internal reference to be shutdown (refe = 0) and an external voltage reference applied to refadj. if either refadc or refdac requires a different or more accurate volt- age, an external reference can be applied directly to refadc or refdac and the corresponding reference buffer must be disabled. applying a digital filter to adc data using the 20-bit accumulator the max1329/MAX1330 incorporate a 20-bit accumula- tor that can sum up to 256 results of the 12-bit adc automatically. see the adc accumulator register sec- tion to set the number of samples to be summed. once the accumulator is full, the acf bit in the status register is asserted. the accumulator provides a digital filtering sync func- tion, with an effective data rate equal to f edr = f s /n where f s is the adc sample rate and n is the number of samples accumulated. there is a notch at every integer multiple of f edr . the following equation provides the transfer function of the filter: figure 35 is a plot showing a notch at 60hz by accumu- lating 256 samples at 15.36ksps. the final step is to read the data in the adc accumulator register and divide by the number of samples that were accumulated. shift the data right for each binary multi- ple of accumulated data. for example, for 256 samples the data should be shifted right eight times. increasing adc resolution using the accumulator with dither the max1329/MAX1330 incorporate an internal dither function that can be used along with the 20-bit accumu- lator to easily increase the resolution of the 12-bit adc to up to 16 bits. the oversampling along with the dither increases the resolution with the penalty of a lower effective data rate. use the following equation to deter- mine the number of samples required to increase the resolution by n number of bits: samples = 2 2n to increase the resolution by 4 bits, from 12 to 16 bits, 256 samples are required. after accumulating the required number of samples, read the data from the adc accumulator register and shift right by 4 bits with the 16 lsbs as the increased resolution result. hf nf f nf f c nf f s s s () sin sin = ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? -50 -40 -45 -30 -35 -20 -25 -15 -5 -10 0 0 120 180 60 240 300 360 420 480 digital-filter transfer function frequency (hz) filter response (db) figure 35. plot of the digital filter with 60hz notch
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 73 using the adc with the adc lt (less-than) and gt (greater-than) digital alarms the adc lt and gt alarms compare the latest adc result to the values programmed in the adc lt alarm and adc gt alarm registers, if enabled, and assert the appropriate gta or lta status bit in the status register once the threshold has been exceeded. the digital alarms can be used as a safeguard during normal adc conversions to signify an event. change the gt and lt alarm thresholds, if needed, when selecting a new mux input channel. the adc can be put into autoconversion mode to continuously convert without user intervention. see the auto<2:0> bits in the adc control register section to enable the auto mode and to program the adc conversion rate. layout, grounding, and bypassing for best performance, use pcbs. do not use wire-wrap boards. board layout should ensure that digital and ana- log signal lines are separated from each other. do not run analog and digital (especially clock) signals parallel to one another or run digital lines underneath the max1329/MAX1330 package. high-frequency noise in the v dd power supply can affect the max1329/MAX1330 performance. bypass the av dd and dv dd supplies with a 0.1f capacitor to gnd, close to the av dd and dv dd pins (see table 32 for recommended capacitor values). minimize capacitor lead lengths for best supply-noise rejection. selector guide part no. of dacs no. of op amps temp sensor accuracy (?) internal reference temp coefficient (ppm/? max) temp range max1329betl+ 2 1 3 75 -40c to +85c MAX1330betl+ 1 2 3 75 -40c to +85c + denotes a lead-free/rohs-compliant package.
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 74 ______________________________________________________________________________________ 12-bit daca refdac refadj refadc refdac 2.50v bandgap 12-bit dacb refdac outb fbb daca fifo outa fba dswb dswa a v = 0.5, 0.8192, 1.0 sclk din dout cs ain1 charge pump dv dd serial i/o ain2 c1a c1b out1 in1- in1+ spdt1 dgnd osw1 av dd upper mux pga ain1 ain2 internal clock and divider temp sensor clkio out1 outb fbb in1- dv dd /4 av dd /4 refadc outa fba adc fifo dither 12-bit adc a v = 1, 2, 4, 8 alarm lower mux agnd refdac temp2 temp3 temp1 voltage supervisors and interrupts rst1 rst2 dpio apio apio1 apio2 apio3 apio4 dpio1 dpio2 dpio3 dpio4 agnd oa1 refadc accumulator sno1 snc1 scm1 spdt2 sno2 snc2 scm2 a v = 0.5, 0.8192, 1.0 max1329 functional diagrams
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 75 12-bit daca refdac refadj refadc refdac 2.50v bandgap out2 in2- daca fifo outa fba osw2 dswa a v = 0.5, 0.8192, 1.0 sclk din dout cs ain1 charge pump dv dd serial i/o ain2 c1a c1b out1 in1- in1+ spdt1 dgnd osw1 av dd upper mux pga ain1 ain2 internal clock and divider temp sensor clkio out1 out2 in2- in1- dv dd /4 av dd /4 refadc outa fba adc fifo dither 12-bit adc a v = 1, 2, 4, 8 alarm lower mux agnd refdac temp2 temp3 temp1 voltage supervisors and interrupts rst1 rst2 dpio apio apio1 apio2 apio3 apio4 dpio1 dpio2 dpio3 dpio4 agnd oa1 refadc accumulator sno1 snc1 scm1 spdt2 sno2 snc2 scm2 a v = 0.5, 0.8192, 1.0 MAX1330 in2+ oa2 functional diagrams (continued)
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor 76 ______________________________________________________________________________________ agnd dgnd dgnd sensor fba outa we re ce outb fbb c dpio2 interrupt output cs sck sclk mosi din miso dout reset rst1 interrupt dpio1 interrupt hclkin clkio 32.768khz xout xin rst2 c1a dv dd av dd v dd c1b 1.8v to 3.6v 3.0v e1 ain1 ain2 2n3904 refadc refadj refdac 33 f 1 f 0.1 f 10 f 1 f 0.01 f 1 f r f 0.1 f max1329 typical operating circuit
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor ______________________________________________________________________________________ 77 ain2 sno2 snc2 refdac outb fbb n.c. fba outa scm2 dpio3 dpio4 dout din cs rst1 rst2 dpio2 dpio1 sno1 scm1 snc1 in1- out1 apio4 apio3 apio2 apio1 dgnd dv dd c1a c1b av dd agnd refadj refadc ain1 clkio thin qfn + max1329 top view sclk in1+ 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 exposed pad? connect to agnd pin configurations ain2 sno2 snc2 refdac out2 in2- in2+ fba outa scm2 dpio3 dpio4 dout din cs rst1 rst2 dpio2 dpio1 sno1 scm1 snc1 in1- out1 apio4 apio3 apio2 apio1 dgnd dv dd c1a c1b av dd agnd refadj refadc ain1 clkio thin qfn + MAX1330 top view sclk in1+ 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 exposed pad? connect to agnd package type package code document no. 40 tqfn-ep t4066-5 21-0141 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages .
max1329/MAX1330 12-/16-bit dass with adc, dacs, dpios, apios, reference, voltage monitors, and temp sensor maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 78 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 8/08 initial release 1 10/08 corrected absolute maximum ratings table 2

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